DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicant’s cancellation of claims 1-20, and submission of new claims 21-40 in “Claims - 10/17/2024” is acknowledged.
This office action considers claims 21-40 are presented and are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (110; Fig 1A; [0016]) = (element 110; Figure No. 1A; Paragraph No. [0016]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference citation may not be preceded by the inventor tag, wherein the other reference citation will carry inventor tag. These conventions are used throughout this document.
Claim 21-22, 24, 26, 28-29. 31-38 and 40 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by You; Wen-Chun et al. (US 20160268499 A1) hereinafter You’499.
Regarding Claim 21. You’499 teaches a memory device (1200; Fig 12; [0057-0058] with MRAM cell 102a; Figs 1a, [0015), comprising (see the entire document, Figs 1a-1b,2, 14A along with 3-13A-14, specifically, as cited below):
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You’499 Figure 1A
a bottom electrode (110; Figs 1a-1b,2, 14A; first cited at Fig 1a; [0016]) above an electrically conductive structure (104), the electrically conductive structure being embedded within an interconnect dielectric material (of 106, a dielectric layer));
a dielectric liner (108a,108b; [0015]) laterally surrounding outer sidewalls of the bottom electrode (110); and
a magnetic tunnel junction stack (MTJ 112; [0016]) above the bottom electrode (110), the magnetic tunnel junction stack (MTJ 112) comprising
a magnetic reference layer (118; [0016]) above the bottom electrode (110),
a tunnel barrier layer (116) above (considered upside down) the magnetic reference layer, and
a magnetic free layer (114, a free layer; [0016]) above (considered upside down) the tunnel barrier layer(116) ,the magnetic free layer being laterally recessed with respect to the tunnel barrier layer, the magnetic free layer surrounded by sidewall spacers (124a,124b; [0119]) to confine an active region (121) formed by the magnetic free layer and the tunnel barrier layer.
Regarding Claim 22. You’499 as applied to the memory device of claim 21, further teaches, (the device) further comprising:
a top electrode (120; [0018]) disposed over the magnetic tunnel junction stack (112).
Regarding Claim 24. You’499 as applied to the memory device of claim 21, further teaches, wherein the top electrode (120) comprises titanium nitride ([0018]).
Regarding Claim 26. You’499 as applied to the memory device of claim 21, further teaches, wherein the dielectric liner (108a,108b; [0015]) is an etch stop layer comprising silicon carbide (SiC; [0015]).
Regarding Claim 28. You’499 as applied to the memory device of claim 21, further teaches, wherein a line that is drawn from an innermost sidewall of the sidewall spacers (12a) a traverses an outer portion of the tunnel barrier layer (116) , the line being perpendicular to an upper surface of the electrically conductive structure (104).
Regarding Claim 29. You’499 teaches a device (1200; Fig 12; [0057-0058] with MRAM cell 102a; Figs 1a, [0015), comprising (see the entire document, Figs 1a-1b,2, 14A along with 3-13A-14, specifically, as cited below):
a bottom electrode (110; Figs 1a-1b,2, 14A; first cited at Fig 1a; [0016]) above an electrically conductive structure (104), the electrically conductive structure being embedded within an interconnect dielectric material (of 106, a dielectric layer));
a dielectric liner (108a,108b; [0015]) laterally surrounding outer sidewalls of the bottom electrode (110);
a low-k dielectric layer (130; Fig 2; [0021]) laterally surrounding outer sidewalls of the dielectric liner (108a/109b);
a magnetic tunnel junction stack (MTJ 112; [0016]) above the bottom electrode (110); and
a top electrode (120) over the magnetic tunnel junction stack (112),
wherein the magnetic tunnel junction stack (112) comprises a magnetic reference layer (118; [0016]) above the bottom electrode (110), a tunnel barrier layer (116) above (considered upside down) the magnetic reference layer, and a magnetic free layer above the tunnel barrier layer, the magnetic free layer (114, a free layer; [0016])being laterally recessed with respect to the tunnel barrier layer, the magnetic free layer surrounded by a sidewall spacer structure (124a,124b; [0119]) to confine an active region ((121) formed by the magnetic free layer and the tunnel barrier layer (116).
Regarding Claim 31. You’499 as applied to the device of claim 29, further teaches, wherein the top electrode (120) has a thickness of about 10 nanometers to about 100 nanometers ([0018]).
Regarding Claim 32. You’499 as applied to the device of claim 29, further teaches, wherein the bottom electrode (110) has a thickness of about 10 nanometers to about 100 nanometers (([0015])).
Regarding Claim 33. You’499 as applied to the device of claim 29, further teaches, wherein the electrically conductive structure (104) comprises a via (BEVA; 0015) or a metal line and comprises aluminum or copper ([0015]).
Regarding Claim 34. You’499 as applied to the device of claim 29, further teaches, wherein a line that is drawn from an innermost sidewall of the sidewall spacer structure (124a,124b; Fig 1A; [0119]) and that is perpendicular (depicted in Fig 1A) to an upper surface of the electrically conductive structure (104) traverses an outer portion of the tunnel barrier layer (116).
Regarding Claim 35. You’499 teaches a device (1200; Fig 12; [0057-0058] with MRAM cell 102a; Figs 1a, [0015), comprising (see the entire document, Figs 1a-1b,2, 14A along with 3-13A-14, specifically, as cited below):
a bottom electrode (110; Figs 1a-1b,2, 14A; first cited at Fig 1a; [0016]) above an electrically conductive structure (104), the electrically conductive structure being embedded within an interconnect dielectric material (of 106, a dielectric layer));
a magnetic tunnel junction stack (MTJ 112; [0016]) above the bottom electrode (110); and
a top electrode (120) over the magnetic tunnel junction stack (112),
wherein the magnetic tunnel junction stack (112) compring a magnetic reference layer (118; [0016]) above the bottom electrode (110), a tunnel barrier layer (116) above (considered upside down) the magnetic reference layer, and a magnetic free layer above the tunnel barrier layer, the magnetic free layer (114, a free layer; [0016])being laterally recessed with respect to the tunnel barrier layer, the magnetic free layer surrounded by sidewall spacers (124a,124b; [0119]) to confine an active region ((121) formed by the magnetic free layer and the tunnel barrier layer; and
wherein an innermost sidewall of the sidewall spacers (124a,124b) lies on a plane that is perpendicular (depicted in Fig 1) to an upper surface of the electrically conductive structure (104), and the plane traverses an outer portion of the tunnel barrier layer (116).
Regarding Claim 36. You’499 as applied to the device of claim 35, further teaches, wherein the top electrode (120) has a thickness of about 10 nanometers to about 100 nanometers ([0018]).
Regarding Claim 37. You’499 as applied to the device of claim 35, further teaches, wherein the bottom electrode (110) has a thickness of about 10 nanometers to about 100 nanometers ([0015]).
Regarding Claim 38. You’499 as applied to the device of claim 35, further teaches, wherein the electrically conductive structure (104) is a metal line or a via (BEVA; 0015) and comprises aluminum or copper ([0015]).
Regarding Claim 40. You’499 as applied to the device of claim 35, further teaches, wherein the top electrode (10) comprises tungsten or titanium nitride ([0018]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over You; Wen-Chun et al. (US 20160268499 A1) hereinafter You’499; in view of LEE; Yong-Kyu et al. (US 20170069827 A1); hereinafter Lee.
Regarding Claim 23. You’499 as applied to the memory device of claim 22, does not expressly disclose, wherein the top electrode (120) comprises tungsten, while discloses ([0018] the top electrode 120 may be a conductive material, such as, for example, titanium nitride, tantalum nitride, titanium, tantalum, or a combination of one or more of the foregoing).
However, in the analogous art, Lee discloses a top electrode 48 of a MTJ element 30 comprises tungsten (Fig 5; [0109-0110]); wherein ([0109]) titanium nitride and/or tungsten can be used as electrode materials of MTJ element for their relative low reactivity (Lee 0109).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Lee’s tungsten containing electrode for the MTJ element of devices of You’499. The substitution would have resulted in the predictable result of low reactive electrode of MTJ element. The claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention.
Claims 25, 27, 30 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over You; Wen-Chun et al. (US 20160268499 A1) hereinafter You’499; in view of Hwang; Kyu-Man et al. (US 2016/0155934 A1); hereinafter Hwang.
Regarding Claim 25. You’499 as applied to the memory device of claim 21, does not disclose expressly, wherein the magnetic tunnel junction stack (MTJ 112) has sidewalls that are angled at an angle of other than 90-degrees as measured relative to a normal line passing through an upper surface of the bottom electrode (110).
However, in the analogous art, Hwang teaches spacer layer 305 may be formed to cover a top surface and a sidewall of the MTJ structure ([0177]), wherein [Fig 2; [0068])the layer 305 comformally covering a MTJ having a slanted outer sidewall (negative slope) and the MTJ structure with slanted sidewalls (negative slope) can prevent short circuit between magnetic material layers of the MTJ.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate Hwang teaching to modify You’499’s sidewall of the magnetic tunnel junction stack (MTJ 112) to have angled at an angle of other than 90-degrees as measured relative to a normal line passing through an upper surface of the bottom electrode (110), since, this modification, at least will prevent short circuit between magnetic material layers of the MTJ ( Hwang [0068]).
Regarding Claims 27, 30, 39. You’499 as applied to the memory device or devices of claims 22 and or 29, 35 respectively, further teaches, (the device) further comprising:
a dielectric protection layer (126a/126b, labelled as capping layer; [0019]) surrounding the top electrode (120) and the magnetic tunnel junction stack (112),
But does not expressly disclose, wherein the dielectric protection layer comprises a slanted outer sidewall and has a flat upper surface extending continuously from over the magnetic tunnel junction stack to over a second magnetic tunnel junction stack.
However, in the analogous art, Hwang teaches spacer layer 305 as protection layer being formed to cover a top surface and a sidewall of the MTJ structure ([0177]), wherein [Fig 2; [0068]) the layer 305 comformally covering a MTJ having a slanted outer sidewall (negative slope) and the MTJ structure with slanted sidewalls (negative slope) can prevent short circuit between magnetic material layers of the MTJ.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate Hwang’s protection layer 305 into You’499’s magnetic tunnel junction stack (MTJ 112) wherein the dielectric protection layer comprises a slanted outer sidewall and has a flat upper surface extending continuously from over the magnetic tunnel junction stack to over a second magnetic tunnel junction stack, since, this modification, at least will prevent short circuit between magnetic material layers of the MTJ ( Hwang [0068]).
Conclusion
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
July 11, 2026
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