DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 18 are objected to because of the following informalities:
Regarding Claim 1, it recites “the meta line” in line 8, wherein it should read “the metal line”.
Regarding Claim 18, it recites “the meta line” in line 3, wherein it should read “the metal line”. Claim 18 also recites “second dielectric features being higher a top surface of the metal line” in line 4, which appears it should read “higher than a top surface” Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11, 12, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chien-Han Chen et al. (US 20200135562 A1; hereinafter Chen).
Regarding Claim 11, Chen discloses a semiconductor structure (see device 100 in Figs. 6, 7, 8, 9, and 10), comprising:
a substrate (101; ¶0013);
a first layer of an interconnect structure formed over the substrate (101), wherein the first layer contains a first dielectric material (103/105; ¶0022) and a first conductive feature (115; ¶0019-¶0021) disposed in the first dielectric material, wherein the first dielectric material (103/105) is higher than the first conductive feature (115) (Fig. 5);
an etch stop layer (117/119; ¶0025) disposed on the first layer of the interconnect structure (Fig. 6); and
a second layer of the interconnect structure formed over the etch stop layer (117/119), wherein the second layer contains a second dielectric material (121; ¶0027) and a second conductive feature (129L/129V; ¶0038 and including the barrier layer 127) disposed in the second dielectric material (Fig. 9),
wherein the second conductive feature (129L/129V) is at least partially aligned with, and electrically coupled to, the first conductive feature (115) (Fig. 9; ¶0034-¶0040).
Regarding Claim 12, Chen discloses the semiconductor structure of claim 11, wherein the first dielectric material is higher than the first conductive feature for a distance from about 50 Å to about 120 Å (about 50 Å; ¶0024).
Regarding Claim 16, Chen discloses the semiconductor structure of claim 11, wherein the second conductive feature (129L/129V) is in physical contact and partially covers a top surface of the first conductive feature (115) (Fig. 9), and the second conductive feature (129L/129V) is in physical contact and partially covers a top surface of the first dielectric material (103/105) (Fig. 9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7-9, 13-15, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chien-Han Chen et al. (US 20200135562 A1; hereinafter Chen) in view of Sanghoon Ahn et al. (US 20210125856 A1; hereinafter Ahn).
Regarding Claim 1, Chen discloses a semiconductor structure (see device 100 in Figs. 6, 7, 8, 9, and 10), comprising:
a substrate (101; ¶0013) having a conductive feature (102; ¶0014) disposed in a top portion of the substrate (101);
a metal line (115; ¶0019-¶0021) above the substrate (101) and in electrical coupling with the conductive feature (102) (¶0022), the metal line (115) having a first metal (¶0019-¶0021);
a dielectric feature (103/105; ¶0022) disposed on a sidewall of the metal line (115), a top surface of the dielectric feature (103/105) being higher than a top surface of the metal line (115);
an etch stop layer (117/119; ¶0025) disposed on the top surface of the dielectric feature (103/105) and the top surface of the metal line (115); and
a via (129V; ¶0034 and including the barrier layer 127) extending through the etch stop layer (117/119) and in physical contact with the top surface of the dielectric feature (103/105) and the top surface of the metal line (115), the via (129V) having a second metal (fill metal; ¶0032).
Chen does not expressly disclose wherein the second metal is different from the first metal.
In the same field of endeavor, Ahn teaches an interconnect structure with two metal layers, the lower layer (Fig. 2; 120; ¶0024 may be ruthenium) and the second/upper metal layer (Fig. 2; 220; ¶0039 may be copper).
It would have been obvious to one of ordinary skill in the art, before the filing date of the claimed invention, to include the first metal and the second metal of Ahn in the known device of Chen. One would have motivation to make this modification because noble metals in the lower layer provide the benefit of corrosion resistance, which enables a high-quality surface for further metal layer deposition, and by using a non-noble metal as the top metal (fill metal of Chen), one may reduce cost to manufacture by using a cheaper metal.
Regarding Claim 2, modified Chen teaches the semiconductor structure of claim 1, wherein the first metal is a noble metal (as modified; Ru), and the second metal is a non-noble metal (as modified; Cu).
Regarding Claim 3, modified Chen teaches the semiconductor structure of claim 2, wherein the first metal is ruthenium (as modified, Ru), and the second metal is copper (as modified, Cu).
Regarding Claim 5, modified Chen teaches the semiconductor structure of claim 1, wherein a bottom surface of the dielectric feature (bottom of 103/105) is below a bottom surface of the metal line (bottom 115) (Fig. 9/10).
Regarding Claim 7, modified Chen teaches the semiconductor structure of claim 1, wherein the etch stop layer (117/119) is conformally deposited on surfaces of the metal line (115) and the dielectric feature (103/105) (Fig. 6).
Regarding Claim 8, modified Chen teaches the semiconductor structure of claim 1, but does not expressly disclose wherein the top surface of the dielectric feature (103/105) is higher than the top surface of the metal line (115) for a vertical distance that is about one fifth to about one third of a thickness of the metal line.
However, Chen discloses in Fig. 5 and ¶0023-¶0024 that this vertical distance (H) is a result effective variable dependent on the etching time. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the result effective variable affecting the distance (H) in order to achieve the desired leakage current and electrical resistance (Chen; ¶0024). MPEP 2144.05
Regarding Claim 9, modified Chen teaches the semiconductor structure of claim 1, but Chen does not expressly disclose further comprising: an air gap trapped in the dielectric feature (103/105).
In the same field of endeavor, Ahn discloses including an air gap (Fig. 1A; AG; ¶0026) in a dielectric feature between adjacent lower metal lines (120; ¶0026). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the air gap of Ahn in the dielectric feature of Chen in order to reduce the parasitic capacitance between the adjacent lower metal lines (Ahn; ¶0026).
Regarding Claim 13, Chen discloses the semiconductor structure of claim 11, but does not expressly disclose further comprising: an air gap trapped in the first dielectric material.
In the same field of endeavor, Ahn discloses including an air gap (Fig. 1A; AG; ¶0026) in a dielectric feature between adjacent lower metal lines (120; ¶0026). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the air gap of Ahn in the dielectric feature of Chen in order to reduce the parasitic capacitance between the adjacent lower metal lines (Ahn; ¶0026).
Regarding Claim 14, Chen discloses the semiconductor structure of claim 11, but does not expressly disclose wherein the first conductive feature includes a noble metal and the second conductive feature includes a non-noble metal.
In the same field of endeavor, Ahn teaches an interconnect structure with two metal layers, the lower layer (Fig. 2; 120; ¶0024 may be ruthenium) and the second/upper metal layer (Fig. 2; 220; ¶0039 may be copper).
It would have been obvious to one of ordinary skill in the art, before the filing date of the claimed invention, to include the first metal and the second metal of Ahn in the known device of Chen. One would have motivation to make this modification because noble metals in the lower layer provide the benefit of corrosion resistance, which enables a high-quality surface for further metal layer deposition, and by using a non-noble metal as the top metal (fill metal of Chen), one may reduce cost to manufacture by using a cheaper metal.
Regarding Claim 15, modified Chen teaches the semiconductor structure of claim 14, wherein the noble metal is selected from Ru, Ir, Rh, Pt, Pd, and Os, (as modified, Ru) and the non-noble metal is selected from Cu, W, Co, Ni, and Al (as modified, Cu).
Regarding Claim 18, Chen discloses a semiconductor structure (see device 100 in Figs. 6, 7, 8, 9, and 10), comprising:
a metal line (115; ¶0019-¶0021) disposed over a substrate (101; ¶0013);
first and second dielectric features (adjacent 103/105; ¶0022) sandwiching the metal line (left 115), top surfaces of the first and second dielectric features being higher than a top surface of the metal line (Fig. 5);
an etch stop layer (117/119; ¶0025) covering the top surfaces of the first and second dielectric features (adjacent 103/105) (Fig. 9); and
a via (left 129V; ¶0034 and including the barrier layer 127) extending through the etch stop layer (117/119) and landing on the top surface of the metal line (115).
Chen does not expressly disclose wherein the metal line (lower) comprises having a noble metal and the via (upper) comprises having a non-noble metal.
In the same field of endeavor, Ahn teaches an interconnect structure with two metal layers, the lower layer (Fig. 2; 120; ¶0024 may be ruthenium) and the second/upper metal layer (Fig. 2; 220; ¶0039 may be copper).
It would have been obvious to one of ordinary skill in the art, before the filing date of the claimed invention, to include the first metal and the second metal of Ahn in the known device of Chen. One would have motivation to make this modification because noble metals in the lower layer provide the benefit of corrosion resistance, which enables a high-quality surface for further metal layer deposition, and by using a non-noble metal as the top metal (fill metal of Chen), one may reduce cost to manufacture by using a cheaper metal.
Regarding Claim 19, modified Chen teaches the semiconductor structure of claim 18, but does not expressly disclose wherein each of the first and second dielectric features traps an air gap therein.
In the same field of endeavor, Ahn discloses including an air gap (Fig. 1A; AG; ¶0026) in adjacent dielectric features surrounding a lower metal line (120; ¶0026). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the air gaps of Ahn in the dielectric features of Chen in order to reduce the parasitic capacitance between other lower metal lines (Ahn; ¶0026).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ahn and Tsai-Jung Ho et al. (US 9548366 B1; hereinafter Ho).
Regarding Claim 4, modified Chen teaches the semiconductor structure of claim 1, wherein the conductive feature (102) includes a source/drain contact (¶0014).
Chen does not expressly disclose the conductive feature also includes a source/drain contact via.
In the same field of endeavor, Ho discloses a similar device (Fig. 16) with a conductive feature comprising a source/drain region (30; C2:L20-L30) in a substrate (20), a source/drain contact (60B; C10:L25-L35), and a source/drain contact via (66B; C11:L1-L15).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the conductive feature of Ho for that of Chen in order to support higher device integration density (Ho; C1:L1-L25).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ahn and Ruilong Xie et al. (US 20220020688 A1; hereinafter Xie).
Regarding Claim 6, modified Chen teaches the semiconductor structure of claim 1, but does not expressly disclose wherein a bottom surface of the metal line is wider than the top surface of the metal line.
In the same field of endeavor, Xie discloses an interconnect structure comprising a metal line (Fig. 2A; 202; ¶0030) with an adjacent dielectric feature (206; ¶0032), wherein a bottom surface of the metal line is wider than the top surface of the metal line (as shown in Fig. 2A and described in ¶0030). The shape of the metal line is a result effective variable of the method of formation (subtractive etching; ¶0030).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the formation method of Xie in the device of Chen, thereby resulting in the claimed shape (Xie; ¶0030), in order to manufacture the device with the desired processing flow/equipment and/or to provide a process flow for a metal line that prevents void formation in the metal lines (Xie; ¶0026).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ahn and Wei-Yang Lee et al. (US 20200127110 A1; hereinafter Lee).
Regarding Claim 10, modified Chen teaches the semiconductor structure of claim 9, but does not expressly disclose wherein the dielectric feature includes a barrier layer and a dielectric core surrounded by the barrier layer, and the air gap divides the dielectric core into a top portion and a bottom portion and exposes the barrier layer in the air gap.
In the same field of endeavor, Lee discloses a semiconductor device (Fig. 8B) comprising a dielectric feature insulating two metal lines (232; ¶0022 and 212; ¶0015), the dielectric feature includes a barrier layer (214/220 both comprising the same material; ¶0016/¶0019) and a dielectric core (252/216a that is positioned between 214/220, wherein 252 and 216a [¶0028] are made of the same silicon oxide material as described in ¶0027/¶0016) surrounded by the barrier layer (252/216a [core] is between and surrounded by 214/220 [barrier] on the sides), and the air gap (250; ¶0024) divides the dielectric core (252/216 between 214/220) into a top portion (252) and a bottom portion (216a) and exposes the barrier layer (214/220) in the air gap (as shown in Fig. 8B and described in ¶0024).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the dielectric feature of Lee for the dielectric feature of Chen because of their art recognized suitability for the intended purpose of electrical isolation between two conductive features and/or to achieve an improvement in lowering stray capacitance compared to solid dielectrics (Lee; ¶0009).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Xie.
Regarding Claim 17, Chen discloses the semiconductor structure of claim 11, but does not expressly disclose wherein the first conductive feature has slanted sidewalls such that a top portion of the first conductive feature is narrower than a bottom portion of the first conductive feature.
In the same field of endeavor, Xie discloses an interconnect structure comprising a metal line (Fig. 2A; 202; ¶0030) with an adjacent dielectric feature (206; ¶0032), wherein a bottom surface of the metal line is wider than the top surface of the metal line (as shown in Fig. 2A and described in ¶0030) with slanted sidewalls. The shape of the metal line is a result effective variable of the method of formation (subtractive etching; ¶0030).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the formation method of Xie in the device of Chen, thereby resulting in the claimed shape (Xie; ¶0030), in order to manufacture the device with the desired processing flow/equipment and/or to provide a process flow for a metal line that prevents void formation in the metal lines (Xie; ¶0026).
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and remediating the claim objections to claim 18.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 20, modified Chen discloses the semiconductor structure of claim 18 (as mapped above), including wherein the first dielectric feature (103/105) includes a first dielectric core (105) and a first barrier layer (113) surrounding the first dielectric core (113 surrounds on the left/right of 105), the second dielectric feature (103/105) includes a second dielectric core (105) and a second barrier layer (113) surrounding the second dielectric core (113 surrounds on the left/right of 105).
However, to the Examiner’s knowledge, the prior art does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including wherein the first barrier layer (113) separates the via from contacting the first dielectric core, and the via is in physical contact with both the second barrier layer and the second dielectric core.
Claim 18 requires the first and second dielectric features to sandwich the metal line, wherein the via lands on a top surface of the metal line. This requires the metal line of Chen to be the left or right 115. As shown in Chen, the dielectric features (103/105) surrounding the metal line (left or right 115) do not both comprise a barrier surrounding a dielectric core, and wherein the first barrier separates the via from the first dielectric core (e.g. between) while the via is in physical contact with both the second barrier layer and the second dielectric core.
Conclusion
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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