DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1-3, 7-13, 17-20, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Deligianni et al., US 2018/0005988 A1.
Claim 1. Deligianni et al., disclose a package (such as the one in fig. 7, [0037-39]) comprising:
-a III-V die comprising:
-a (111) semiconductor substrate (item 402),
-and a III-V based n-type transistor at a surface of the (111) semiconductor substrate (as noted, by definition, in a transistor, P-type and N-type refer to the type of semiconductor material used to create the layers of the device), at a surface of a (111) semiconductor substrate (item 402),
-and a Complementary Metal-Oxide-Semiconductor (CMOS) die physically bonding to the III- V die, the CMOS die comprising:
-a (100) semiconductor substrate (as explained above),
-an n-type transistor on the (100) semiconductor substrate (the same manner, as explained above),
-and a p-type transistor on the (100) semiconductor substrate (as noted, by definition, in a transistor, P-type and N-type refer to the type of semiconductor material used to create the layers of the device), at a surface of a (111) semiconductor substrate (item 402).
Claims 9, and 19-20. Deligianni et al., disclose a package (such as the one in fig. 7, [0037-39]) comprising:
-a III-V die comprising:
-a (111) semiconductor substrate (item 402),
-a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate (as noted, by definition, in a transistor, P-type and N-type refer to the type of semiconductor material used to create the layers of the device), at a surface of a (111) semiconductor substrate (item 402),
-and a first electrical connector (item 304) connected to the III-V based n-type transistor,
-and a Complementary Metal-Oxide-Semiconductor (CMOS) die directly bonding to the III-V die (this limitation would read through [0040] wherein is disclosed as described above, these (second) bond pads 504 correspond to the (first) bond pads 304 on the Si CMOS wafer and will be used to bond the wafers together (in a face-to-face manner), the CMOS die comprising:
-a (100) semiconductor substrate (as explained above),
-a p-type transistor at a surface of the (100) semiconductor substrate (the same manner, as explained above),
-and a second electrical connector (item 504) connecting to the p-type transistor, wherein the first electrical connector and the second electrical connector interconnect the III-V based n-type transistor and the p-type transistor (as described above, these (second) bond pads 504 correspond to the (first) bond pads 304 on the Si CMOS wafer and will be used to bond the wafers together (in a face-to-face manner).
Claims 2, 3, 12 and 13. Deligianni et al., disclose the package of claims 1, 9, wherein the III-V die is over the CMOS die, and the package further comprises: a through-via in the III-V die (this limitation would through [0053] of Deligianni, wherein is disclosed connections between the CMOS transistors and the magnetic inductor are provided by way of one or more through silicon vias (or TSVs));
-a thermal interface material over and physically contacting the through-via (as [0052] disclose that it is also possible to utilize metal-metal bonds to integrate the chips),
-and a heat sink over and joined to the thermal interface material (this limitation would read through [0051, fig. 12] of Deligianni, wherein is disclosed a heat sink 1204 may also be employed in the packed device, as known in the art).
Claim 7. Deligianni et al., disclose the package of claim 1, wherein the CMOS die comprises an additional p-type transistor, and wherein the III-V based n-type transistor is directly connected to the additional p-type transistor. This limitation would read through [0038] of Deligianni, wherein is disclosed a substrate 302 and an active layer on the substrate 402 in which one or more GaN transistor switches are formed.
Claim 8. Deligianni et al., disclose the package of claim 1, wherein the III-V based n-type transistor in the III-V die is directly connected to an additional p-type transistor in the CMOS die to form an inverter (this limitation would read through [0050] of Deligianni, wherein is disclosed arranging one of the chips in the converter structure in the cavity, the solder bumps 1102 bonding the chips together can also be leveraged to make connections with inter-packaging metal wiring to the solder bumps 1204 of the BGA).
Claims 10, 17. Deligianni et al., disclose the package of claim 9, wherein the III-V based n-type transistor and the p- type transistor are directly interconnected to form a functional circuit (this limitation would read through [0042] of Deligianni, wherein is disclosed for example, solder bumps 702 are then formed on either the (first) bond pads 304 or the (second) bond pads 504, and the Si CMOS chip and the GaN switch chip are then bonded in a face-to-face manner via a solder bond between the bond pads 304 and 504. See FIG. 7. Namely, to enable this face-to-face bonding, one of the chips (in this example the Si CMOS chip) is flipped such that the fronts of the Si CMOS and GaN switch chips are facing one another, and such that the solder bumps 702 can interconnect the two chips. As noted, in a package device, a functional circuit means the internal electrical system is not just physically assembled but is electrically complete, operational, and meets its design performance goals under real operating conditions.
Claims 11, 18. Deligianni et al., disclose the package of claim 10, wherein the III-V based n-type transistor and the p- type transistor form an inverter (this limitation would read through [0050] of Deligianni, wherein is disclosed arranging one of the chips in the converter structure in the cavity, the solder bumps 1102 bonding the chips together can also be leveraged to make connections with inter-packaging metal wiring to the solder bumps 1204 of the BGA).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
5. Claim(s) 4, 14, is/are rejected under 35 U.S.C. 103 as being unpatentable over Deligianni et al., US 2018/0005988 A1, in view of Roberts et al., US 2016/0380090 A1.
Claims 4 and 14. Deligianni et al., disclose the method of claims 1, 9. Deligianni appears to not disclose “further comprising dispensing an underfill between, and in physical contact with, the III-V die and the CMOS die”.
Roberts teaches dispensing an underfill (item 130, fig. 3, [0102]) into a gap between the III-V die and the CMOS die”. Deligianni et al., and Roberts are analogous art because they are from the same field of endeavor as applicant’s invention. At the time of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate an underfill material into a gap between the III-V die and the CMOS die as taught by Roberts to reduce risk of damage during conventional wafer post-processing, which also mechanically strengthens the structure of the device.
6. Claim(s) 6, 16, is/are rejected under 35 U.S.C. 103 as being unpatentable over Deligianni et al., US 2018/0005988 A1, in view of Doczy et al., US 2006/0030104 A1.
With respect to claims 6 and 16. Deligianni et al., disclose the method of claims 1, 9, above.
Deligianni et al., appear to not specify wherein the III-V die is free from p-type transistors.
However, the structure of fig. 6 of Doczy et al., discloses the transistors after a selective dry etch is performed to remove the p-type polysilicon without removing the n-type metal gate. At the time of the invention, it would have been obvious to a person of ordinary skill in the art to remove the p-type polysilicon without removing the n-type metal gate, because the scientists concluded that the diffusivity of hydrogen in p-type poly-Si is lower than in n-type, which prevents the accumulation of excess hydrogen around the oxide which deteriorates the passivation quality. “The results extend our understanding of the firing effect on poly-Si/SiOx structures, which may help to further improve the performance of doped poly-Si contacts,” they added (see emiliano.bellini@pv-magazine.com).
7. Claim(s) 5, 15, is/are rejected under 35 U.S.C. 103 as being unpatentable over Deligianni et al., US 2018/0005988 A1, in view of Chang et al., US 2014/0035158 A1.
With respect to claims 5 and 15. Deligianni et al., disclose the method of claims 1, 9, above.
Deligianni et al., appear to not specify wherein the III-V die and the CMOS die are bonded through hybrid bonding.
However, the structure of fig. 2C of Chang discloses the fabrication process of a CMOS device wafer 124 is bonded to device substrate 110 using conductive wafer bonding. In this exemplary embodiment, wafer bonding methods such as, for example, fusion bonds, eutectic bonds, and/or hybrid bonds may be utilized. At the time of the invention, it would have been obvious to a person of ordinary skill in the art to use hybrid bonding technique to bond a III‑V die to a CMOS die is driven by the need for extreme I/O density, superior electrical performance, reliability, and thermal management in heterogeneous 3D systems. It overcomes the limitations of solder bumps and wire bonding, making it ideal for high‑performance, high‑bandwidth, and power‑efficient III‑V–CMOS hybrids.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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