DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/24/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Objections
Claim 19 and 20 are objected to because of the following informalities:
Claims 19 and 20 depend on claim 1, which causes conflicting relationship between the channel widths of claim 1. If claims 19 and 20 depend from claim 18, that might resolve the conflict.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11, 16 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites “the width of the first rectangular area” and “a width of the second rectangular area”. Claim 11 depends on claim 9, which recites a first rectangular area and a second rectangular area but does not recite the width of the first rectangular area. A width of each rectangular area recited in claim 10, from which claim 11 does not depend. Therefore, there is insufficient antecedent basis for these limitations.
Claim 16 recites “the first pull-down GAA transistor include first source/drain features having the first channel width, the first pass-gate GAA transistor include second source/drain features having the second channel width”. However, Claim 16 depends on claim 12, which recites “each of the first and the second pass-gate GAA transistors has a first channel width, each of the first and the second pull-down GAA transistors has a second channel width”. It cannot be determined whether claim 16 is intended to reverse the channel widths of claim 12 or contains an error. Furthermore, in claim 16 channel width is attributed to the source/drain features. Source/drain feature has no channel, therefore it is unclear what the applicant meant by “first source/drain features having the first channel width, and second source/drain features having the second channel width”. Therefore, the scope of the claim is unclear.
Claim 19 recites “a ratio of the sixth channel width to the third channel width is in a range of 1.05 to 1.5.” Claim 1, upon which claim 19 depends, the third channel width is the channel width of the third and fourth pass-gate GAA transistors of the second SRAM cell, and the sixth channel width is the channel width of the third and fourth pull-up GAA transistors of the same cell. Claim 19 requires the channel width of the third and fourth pull-up GAA transistors wider than the channel width of the third and fourth pass-gate GAA transistors, which is inverse of the relation specification ¶ [0042] recites “In an embodiment, a ratio of W6 to W4 (the alpha ratio of the high-current SRAM cell 154) is less than about 0.7. For example, a ratio of W4 to W6 may be in a range of 1.5 to 5 for write margin improvements.” Therefore, it is unclear if the dependency of claim 19 is correct or it depends on claim 12 or claim 18, in which the third and sixth channel widths are the pull-up channel widths of the first and second SRAM cells respectively.
Appropriate corrections are required.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1-20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 recites “the second channel width is greater than the first channel width;” and “the sixth channel width is greater than the fifth channel width.” Claims 12 and 20 recite “each of the fourth and the fifth channel widths are greater than the second channel width, wherein the sixth channel width is greater than the third channel width.” The widths relationships are open ended and the specification only discloses a single range a ratio of the pull-down channel width to the pass gate-gate channel width is “in a range of 1.05 to 1.5” and a ratio of the second cell’s pull-up channel width to the first cell’s pull-up channel widths “in a range of 1.05 to 1.5”. Therefore, the Applicant has not shown to have the claimed open ended widths relationships genus. See MPEP 2163 “An original claim may lack written description support when (1) the claim defines the invention in functional language specifying a desired result but the disclosure fails to sufficiently identify how the function is performed or the result is achieved or (2) a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. See Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1349-50 (Fed. Cir. 2010) (en banc). The written description requirement is not necessarily met when the claim language appears in ipsis verbis in the specification. "Even if a claim is supported by the specification, the language of the specification, to the extent possible, must describe the claimed invention so that one skilled in the art can recognize what is claimed. The appearance of mere indistinct words in a specification or a claim, even an original claim, does not necessarily satisfy that requirement."Enzo Biochem, Inc. v. Gen-Probe, Inc., 323 F.3d 956, 968, 63 USPQ2d 1609, 1616 (Fed. Cir. 2002).”
Claims 2-11 and 19-20 inherit the deficiency, based on their dependency on claim 1.
Claims 13-17 inherit the deficiency, based on their dependency on claim 12.
Claim 19 recites “a ratio of the sixth channel width to the third channel width is in a range of 1.05 to 1.5.” Claim 1, upon which claim 19 depends, the third channel width is the channel width of the third and fourth pass-gate GAA transistors of the second SRAM cell, and the sixth channel width is the channel width of the third and fourth pull-up GAA transistors of the same cell. Claim 19 requires the channel width of the third and fourth pull-up GAA transistors wider than the channel width of the third and fourth pass-gate GAA transistors, which is inverse of the relation specification ¶ [0042] recites “In an embodiment, a ratio of W6 to W4 (the alpha ratio of the high-current SRAM cell 154) is less than about 0.7. For example, a ratio of W4 to W6 may be in a range of 1.5 to 5 for write margin improvements.” No embodiments described pull-up channel exceeds its pass-gate channel. Therefore, claim 19 lacks written description support.
Appropriate corrections are required.
Nonstatutory Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5, 9-12, 15 and 18 are rejected on the ground of nonstatutory double patenting (Anticipation) as being unpatentable over claims 1-3, 5, 7, 13-14 and 18-19 of US 12127387 B2 “Patent-387”
Claim limitations of Instant Application
Claim limitations of US 12127387 B2
Claim 1,
A semiconductor structure, comprising:
a first SRAM cell over a substrate,
the first SRAM cell includes a first inverter having a first pull-up GAA transistor coupled to a first pull-down GAA transistor and a second inverter having a second pull-up GAA transistor coupled to a second pull-down GAA transistor, the first and the second inverters are cross coupled to form first data storage nodes,
the first SRAM cell further includes first and second pass-gate GAA transistors for accessing the first data storage nodes,
each of the first and the second pass-gate GAA transistors has a first channel width, each of the first and the second pull-down GAA transistors has a second channel width, and the second channel width is greater than the first channel width; and
a second SRAM cell over the substrate, the second SRAM cell includes a third inverter having a third pull-up GAA transistor coupled to a third pull-down GAA transistor and a fourth inverter having a fourth pull-up GAA transistor coupled to a fourth pull-down GAA transistor, the third and the fourth inverters are cross-coupled to form a second data storage nodes,
the second SRAM cell further includes third and fourth pass-gate GAA transistors for accessing the second data storage nodes,
each of the third and the fourth pass-gate GAA transistors has a third channel width, each of the third and the fourth pull-down GAA transistors has a fourth channel width, and the third channel width is substantially the same as the fourth channel width,
wherein the fourth channel width is larger than the second channel width,
wherein each of the first and the second pull-up GAA transistors has a fifth channel width, each of the third and the fourth pull-up GAA transistors has a sixth channel width, and the sixth channel width is greater than the fifth channel width.
Claim 1,
A semiconductor structure, comprising:
a substrate; and first and second SRAM cells over the substrate,
the first SRAM cell includes a first inverter having a first pull-up GAA transistor coupled to a first pull-down GAA transistor a second inverter having a second pull-up GAA transistor coupled to a second pull-down GAA transistor, the first and the second inverters are cross coupled to form first data storage nodes,
the first SRAM cell further includes first and second pass-gate GAA transistors for accessing the first data storage nodes,
each of the first and the second pass-gate GAA transistors has a first channel width, each of the first and the second pull-down GAA transistors has a second channel width, and a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5,
wherein the second SRAM cell includes a third inverter having a third pull-up GAA transistor coupled to a third pull-down GAA transistor and a fourth inverter having a fourth pull-up GAA transistor coupled to a fourth pull-down GAA transistor, the third and the fourth inverters are cross-coupled to form a second data storage nodes,
the second SRAM cell further includes third and fourth pass-gate GAA transistors for accessing the second data storage nodes,
each of the third and the fourth pass-gate GAA transistors has a third channel width, each of the third and the fourth pull-down GAA transistors has a fourth channel width, and the third and the fourth channel widths are substantially same, and
wherein the fourth channel width is larger than the second channel width, and
wherein each of the first and the second pull-up GAA transistors has a fifth channel width, each of the third and the fourth pull-up GAA transistors has a sixth channel width, and a ratio of the sixth channel width to the fifth channel width is in a range of 1.05 to 1.5.
Claim limitations of Instant Application
Claim limitations of US 12127387 B2
Claim 2,
The semiconductor structure of claim 1,
wherein a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5.
Claim 1, (Limitation 1D)
a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5,
Claim 3,
The semiconductor structure of claim 1,
wherein a ratio of the sixth channel width to the fifth channel width is in a range of 1.05 to 1.5.
Claim 1, (Limitation 1I)
a ratio of the sixth channel width to the fifth channel width is in a range of 1.05 to 1.5.
Although the claims at issue are not identical, they are not patentably distinct from each other for the following reasons.
Regarding Claim 1, Patent-387 claim 1 recites a first SRAM cell and a second SRAM cell over a substrate, each with cross-coupled inverters of pull-up and pull-down GAA transistors, with the same first through six channel widths as instant claim 1; the third and fourth channel widths substantially the same; and the fourth channel width is larger than the second channel width. Instant claim 1 requires the second channel width to be greater than the first and the sixth channel width is greater than the fifth channel width. Patent-387 claim 1 requires each of those ratios to be 1.05 to 1.5, which necessarily satisfies “greater than”. Patent-387 claim 1 is therefore a species falling within the instant claim 1 and instant claim 1 is anticipated by it.
If a generic claim is presented in a separate application after the issuance of a patent claiming one or more species within the scope of the generic claim, the Office may reject the generic claim on the grounds of nonstatutory double patenting when the patent and application have at least one common (joint) inventor and/or are either (1) commonly assigned/owned or (2) non-commonly assigned/owned but subject to a joint research agreement as set forth in 35 U.S.C. 102(c) or pre-AIA 35 U.S.C. 103(c)(2) and (3). See MPEP § 804. Applicant may overcome such a rejection by filing a terminal disclaimer. See In re Goodman, 11 F.3d 1046, 1053, 29 USPQ2d 2010, 2016 (Fed. Cir. 1993); In re Braithwaite, 379 F.2d 594, 154 USPQ 29 (CCPA 1967).
Regarding Claim 2, recite a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5, which is recited in Patent-387 claim 1 (Limitation 1D). Therefore, Patent-387 claim 1 anticipates instant claims 2.
Regarding Claim 3, recite a ratio of the sixth channel width to the fifth channel width is in a range of 1.05 to 1.5 which are recited in Patent-387 claim 1 (Limitation 1I). Therefore, Patent-387 claim 1 anticipates instant claims 3.
Claim limitations of Instant Application
Claim limitations of US 12127387 B2
Claim 4,
The semiconductor structure of claim 1,
wherein a ratio of the sixth channel width to the fifth channel width is in a range of 1.05 to 1.5.
Claim 2,
The semiconductor structure of claim 1,
wherein a ratio of the sixth channel width to the fifth channel width is in a range of 1.05 to 1.5.
Claim 5,
The semiconductor structure of claim 1, further comprising:
first bit lines disposed in a first metal layer and connected to the first SRAM cell; and
second bit lines disposed in the first metal layer and connected to the second SRAM cell,
wherein the first bit lines have a first width, the second bit lines have a second width, and
a ratio of the second width to the first width is greater than 1.2.
Claim 7,
The semiconductor structure of claim 1, wherein
the first SRAM cell further includes a first bit line conductor and a first bit line bar conductor disposed in a first-level metal layer;
the second SRAM cell further includes a second bit line conductor and a second bit line bar conductor disposed in the first-level metal layer;
each of the first bit line conductor and the first bit line bar conductor has a first metal line width; each of the second bit line conductor and the second bit line bar conductor has a second metal line width; and
a ratio of the second metal line width to the first metal line width is greater than 1.2.
Regarding Claim 4, recited limitations are the same as those of Patent-387 claim 2.
Regarding Claim 5, reciting generic bit lines in a first metal layer which is bit line and bit line bar conductors in a first level meatal layer of Patent-387 claim 7.
Claim 6-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 and 7 of US 12127387 B2 “Patent-387” in view of Liaw, Jhon Jhy (US 20200135740 A1) “Liaw”.
Claim limitations of Instant Application
Claim limitations of US 12127387 B2
Claim 6,
The semiconductor structure of claim 1, wherein
the first SRAM cell is electrically connected to a write-assist circuit while
the second SRAM cell is not.
Claim 9,
The semiconductor structure of claim 1, further comprising
a write-assist circuit coupled to the first SRAM cell.
Not recited
Claim 7,
The semiconductor structure of claim 6, further comprising:
first bit lines disposed in a first metal layer and electrically connected to the first and the second pass-gate GAA transistors,
wherein the write-assist circuit includes voltage generator for driving the first bit lines to a voltage below a ground reference voltage.
Claim 7,
The semiconductor structure of claim 1, wherein
the first SRAM cell further includes a first bit line conductor and a first bit line bar conductor disposed in a first-level metal layer;
Not Recited
Regarding Claim 6, Patent-387 claim 9 recites a write-assist circuit coupled to the first SRAM cell as instant claim 6;
However, Patent-387 claim 9 does not disclose, the second SRAM cell is not electrically connected to a write-assist circuit, and the write-assist circuit includes voltage generator for driving the first bit lines to a voltage below a ground reference voltage.
In the similar field of endeavor of semiconductor devices, Liaw Figs. 1-6, discloses the second SRAM cell is not electrically connected to a write-assist circuit (“In some embodiments of the present disclosure, a write assist circuitry may be included in a first peripheral circuit of the first type SRAM cells 200 or a macro consisting of the first type SRAM cells 200. In these embodiments, such write assist circuitry is not included in or omitted from a second peripheral circuit of the second type SRAM cells 300 or a macro consisting of the second type SRAM cells 300.” ¶ [0041]);
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the first SRAM cell of Patent-387 by omitting the write assist for the second SRAM as Liaw in order to made possible by either the wider nanosheet channels in the second type SRAM cells 300 or the wider bit lines in the second type SRAM cells 300, or both (Liaw ¶ [0041])
Regarding Claim 7, Patent-387 claim 7 further recites bit line conductor and a first bit line bar conductor disposed in a first-level metal layer.
However, Patent-387 claim 9 does not disclose, the second SRAM cell is not electrically connected to a write-assist circuit, and the write-assist circuit includes voltage generator for driving the first bit lines to a voltage below a ground reference voltage.
In the similar field of endeavor of semiconductor devices, Liaw Figs. 1-6, discloses the second SRAM cell is not electrically connected to a write-assist circuit (“In some embodiments of the present disclosure, a write assist circuitry may be included in a first peripheral circuit of the first type SRAM cells 200 or a macro consisting of the first type SRAM cells 200. In these embodiments, such write assist circuitry is not included in or omitted from a second peripheral circuit of the second type SRAM cells 300 or a macro consisting of the second type SRAM cells 300.” ¶ [0041]); the write-assist circuit includes voltage generator for driving the first bit lines to a voltage below a ground reference voltage (“the write assist circuitry may assist writing of an SRAM cell by having negative bit lines, raising Vss, reducing Vdd, or boosting word line (WL).” ¶ [0041])
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the first SRAM cell of Patent-387 by including the write-assist circuit includes voltage generator for driving the first bit lines to a voltage below a ground reference voltage as Liaw in order to made possible by either the wider nanosheet channels in the second type SRAM cells 300 or the wider bit lines in the second type SRAM cells 300, or both (Liaw ¶ [0041])
Claims 9 is rejected on the ground of nonstatutory double patenting (Anticipation) as being unpatentable over claims 3, of US 12127387 B2 “Patent-387”
Claim limitations of Instant Application
Claim limitations of US 12127387 B2
Claim 9,
The semiconductor structure of claim 1, wherein
the first SRAM cell occupies a first rectangular area, and the second SRAM cell occupies a second rectangular area from a top view, and
the second rectangular area is bigger than the first rectangular area.
Claim 3,
The semiconductor structure of claim 1, wherein
the first SRAM cell occupies a first rectangular area, and the second SRAM cell occupies a second rectangular area from a top view,
a width of the first rectangular area is substantially same as a width of the second rectangular area, and a ratio of a length of the second rectangular area to a length of the first rectangular area is greater than or equal to 1.05.
Regarding Claim 9, Patent-387 claim 3 recited first and second rectangular areas and a ratio of a length of the second rectangular area to a length of the first rectangular area is greater than or equal to 1.05 which necessarily makes the second rectangular area is bigger than the first rectangular area. Therefore, Patent-387 claim 3 anticipates instant claim 9.
Claims 10-11 are rejected on the ground of nonstatutory double patenting (Anticipation) as being unpatentable over claims 3 and 5, of US 12127387 B2 “Patent-387”
Claim 10,
The semiconductor structure of claim 9, wherein
a width of the first rectangular area is substantially same as a width of the second rectangular area, and
a ratio of a length of the second rectangular area to a length of the first rectangular area is greater than or equal to 1.05.
Claim 3,
The semiconductor structure of claim 1, wherein the first SRAM cell occupies a first rectangular area, and the second SRAM cell occupies a second rectangular area from a top view,
a width of the first rectangular area is substantially same as a width of the second rectangular area, and
a ratio of a length of the second rectangular area to a length of the first rectangular area is greater than or equal to 1.05.
Claim 11,
The semiconductor structure of claim 9, wherein
a ratio of a length of the first rectangular area to the width of the first rectangular area is greater than 2, and
a ratio of a length of the second rectangular area to a width of the second rectangular area is greater than 2.5.
Claim 5,
The semiconductor structure of claim 3, wherein
a ratio of the length of the first rectangular area to the width of the first rectangular area is greater than 2, and
a ratio of the length of the second rectangular area to the width of the second rectangular area is greater than 2.5.
Regarding Claim 10, recited limitations are the same as those of Patent-387 claim 3. Therefore, Patent-387 claims 3 anticipates instant claim 10.
Regarding Claim 11 recited limitations are the same as those of Patent-387 claim 5. Therefore, Patent-387 claim 5 anticipates instant claim 11.
Claim limitations of Instant Application
Claim limitations of US 12127387 B2
Claim 12,
A semiconductor structure, comprising:
a substrate;
an array of first SRAM cells over the substrate, wherein each of the first SRAM cells includes a first inverter having a first pull-up GAA transistor coupled to a first pull-down GAA transistor and a second inverter having a second pull-up GAA transistor coupled to a second pull-down GAA transistor, the first and the second inverters are cross-coupled to form first data storage nodes,
each of the first SRAM cells further includes first and second pass-gate GAA transistors for accessing the first data storage nodes,
each of the first and the second pass-gate GAA transistors has a first channel width, each of the first and the second pull-down GAA transistors has a second channel width, and the second channel width is greater than the first channel width, and each of the first and the second pull-up GAA transistors has a third channel width; and
an array of second SRAM cells over the substrate, wherein each of the second SRAM cells includes a third inverter having a third pull-up GAA transistor coupled to a third pull-down GAA transistor and a fourth inverter having a fourth pull-up GAA transistor coupled to a fourth pull-down GAA transistor, the third and the fourth inverters are cross-coupled to form second data storage nodes,
each of the second SRAM cells further includes third and fourth pass-gate GAA transistors for accessing the second data storage nodes,
each of the third and the fourth pass-gate GAA transistors has a fourth channel width, each of the third and the fourth pull-down GAA transistors has a fifth channel width, and each of the third and the fourth pull-up GAA transistors has a sixth channel width,
wherein the fourth channel width and the fifth channel width are both greater than second channel width,
wherein the sixth channel width is greater than the third channel width.
In claim 15
Claim 13,
A semiconductor structure, comprising:
a substrate; and first and second SRAM macros over the substrate,
wherein the first SRAM macro includes an array of first SRAM cells, each of the first SRAM cells includes a first inverter having a first pull-up GAA transistor coupled to a first pull-down GAA transistor and a second inverter having a second pull-up GAA transistor coupled to a second pull-down GAA transistor, the first and the second inverters are cross-coupled to form a first data storage nodes,
each of the first SRAM cells further includes first and second pass-gate GAA transistors for accessing the first data storage nodes,
each of the first and the second pass-gate GAA transistors has a first channel width, each of the first and the second pull-down GAA transistors has a second channel width, a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5, and each of the first and the second pull-up GAA transistors has a third channel width,
wherein the second SRAM macro includes an array of second SRAM cells, each of the second SRAM cells includes a third inverter having a third pull-up GAA transistor coupled to a third pull-down GAA transistor and a fourth inverter having a fourth pull-up GAA transistor coupled to a fourth pull-down GAA transistor, the third and the fourth inverters are cross-coupled to form a second data storage nodes,
each of the second SRAM cells further includes third and fourth pass-gate GAA transistors for accessing the second data storage nodes,
each of the third and the fourth pass-gate GAA transistors has a fourth channel width, each of the third and the fourth pull-down GAA transistors has a fifth channel width, and each of the third and the fourth pull-up GAA transistors has a sixth channel width,
wherein a ratio of the fifth channel width to the second channel width is in a range of 1.2 to 5, and
a ratio of the sixth channel width to the third channel width is in a range of 1.05 to 1.5 and,
wherein the first SRAM macro further includes an array of write-assist circuits that are coupled to the array of the first SRAM cells.
Claim 15, The semiconductor structure of claim 12, further comprising
an array of write-assist circuits that are coupled to the array of the first SRAM cells.
Claim 13, (13 J)
wherein the first SRAM macro further includes an array of write-assist circuits that are coupled to the array of the first SRAM cells.
Regarding Claim 12 and 15, Patent-387 claim 13 recites arrays of first SRAM cells and a second SRAM cells over a substrate, with the same cell structure and first through six channel widths as instant claim 12; a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5 (therefore, second channel width is greater than the first channel width); a ratio of the fifth channel width to the second channel width is in a range of 1.2 to 5 (therefore, fifth channel width is greater than the second channel width); a ratio of the sixth channel width to the third channel width is in a range of 1.05 to 1.5 (therefore, sixth channel width is greater than the third channel width); and an array of write-assist circuits coupled to the array of the first SRAM cells (which is recited in instant claim 15). Therefore, Patent-387 claim 13 anticipate instant claim 12 and 15.
Claim limitations of Instant Application
Claim limitations of US 12127387 B2
Claim 18,
A semiconductor structure, comprising:
a substrate;
an array of first SRAM cells over the substrate, wherein each of the first SRAM cells includes a first inverter having a first pull-up GAA transistor coupled to a first pull-down GAA transistor and a second inverter having a second pull-up GAA transistor coupled to a second pull-down GAA transistor, the first and the second inverters are cross-coupled to form first data storage nodes,
each of the first SRAM cells further includes first and second pass-gate GAA transistors for accessing the first data storage nodes,
each of the first and the second pass-gate GAA transistors has a first channel width, each of the first and the second pull-down GAA transistors has a second channel width, a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5, and each of the first and the second pull-up GAA transistors has a third channel width;
an array of second SRAM cells over the substrate, wherein each of the second SRAM cells includes a third inverter having a third pull-up GAA transistor coupled to a third pull-down GAA transistor and a fourth inverter having a fourth pull-up GAA transistor coupled to a fourth pull-down GAA transistor, the third and the fourth inverters are cross-coupled to form second data storage nodes,
each of the second SRAM cells further includes third and fourth pass-gate GAA transistors for accessing the second data storage nodes,
each of the third and the fourth pass-gate GAA transistors has a fourth channel width, each of the third and the fourth pull-down GAA transistors has a fifth channel width, and each of the third and the fourth pull-up GAA transistors has a sixth channel width;
first bit lines disposed in a first metal layer and connected to the array of the first SRAM cells; and second bit lines disposed in the first metal layer and connected to the array of the second SRAM cells, wherein the first bit lines have a first width, the second bit lines have a second width, and a ratio of the second width to the first width is greater than 1.2,
wherein each of the fourth and the fifth channel widths are greater than the second channel width,
wherein the sixth channel width is greater than the third channel width.
Claim 18,
A semiconductor structure, comprising:
a substrate; and first and second SRAM macros over the substrate,
wherein the first SRAM macro includes an array of first SRAM cells, each of the first SRAM cells includes a first inverter having a first pull-up GAA transistor coupled to a first pull-down GAA transistor and a second inverter having a second pull-up GAA transistor coupled to a second pull-down GAA transistor, the first and the second inverters are cross-coupled to form a first data storage nodes,
each of the first SRAM cells further includes first and second pass-gate GAA transistors for accessing the first data storage nodes,
each of the first and the second pass-gate GAA transistors has a first channel width, each of the first and the second pull-down GAA transistors has a second channel width, a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5, and each of the first and the second pull-up GAA transistors has a third channel width,
wherein the second SRAM macro includes an array of second SRAM cells, each of the second SRAM cells includes a third inverter having a third pull-up GAA transistor coupled to a third pull-down GAA transistor and a fourth inverter having a fourth pull-up GAA transistor coupled to a fourth pull-down GAA transistor, the third and the fourth inverters are cross-coupled to form a second data storage nodes,
each of the second SRAM cells further includes third and fourth pass-gate GAA transistors for accessing the second data storage nodes,
each of the third and the fourth pass-gate GAA transistors has a fourth channel width, each of the third and the fourth pull-down GAA transistors has a fifth channel width, and each of the third and the fourth pull-up GAA transistors has a sixth channel width,
wherein the first SRAM macro further includes first bit line conductors disposed in a first-level metal layer, the second SRAM macro further includes second bit line conductors disposed in the first-level metal layer, each of the first bit line conductors has a first metal line width, each of the second bit line conductors has a second metal line width, and a ratio of the second metal line width to the first metal line width is greater than 1.2.
wherein a ratio of the fifth channel width to the second channel width is in a range of 1.2 to 5, and
a ratio of the sixth channel width to the third channel width is in a range of 1.05 to 1.5 and,
Regarding Claim 18, Patent-387 claim 18 recites arrays of first SRAM cells and a second SRAM cells over a substrate, with the same cell structure and first through six channel widths as instant claim 18; a ratio of the fifth channel width to the second channel width is in a range of 1.2 to 5 (therefore, fifth channel width is greater than the second channel width); a ratio of the sixth channel width to the third channel width is in a range of 1.05 to 1.5 (therefore, sixth channel width is greater than the third channel width). Therefore, Patent-387 claim 18 anticipates instant claim 18.
Claim 16-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US 12127387 B2 “Patent-387” in view of Liaw, Jhon Jhy (US 20200135740 A1) “Liaw” further in view of KWON; DAE-JIN (US 20170148505 A1) “KWON et al.”.
Claim limitations of Instant Application
Claim limitations of US 12127387 B2
Claim 16, The semiconductor structure of claim 12, wherein
the first pull-down GAA transistor include first source/drain features having the first channel width,
the first pass-gate GAA transistor include second source/drain features having the second channel width, and
the first source/drain features interfaces the second source/drain features.
None
Claim 17, The semiconductor structure of claim 16, further comprising a metal feature landing on where the first source/drain features interface the second source/drain features.
None
Regarding Claim 16 and 17, Patent-387 claims 13-14 discloses the limitations of claim 12. Patent-387 claims 13-14 further recite, first pull-down and first pass-gate GAA transistors of different channel widths.
However, Patent-387 claims 13-14 do not disclose, the first source/drain the second source/drain features, the first source/drain features interfaces the second source/drain features and a metal feature landing on where the first source/drain features interface the second source/drain features.
In the similar field of endeavor of semiconductor devices, Liaw Figs. 1-6, discloses the first source/drain the second source/drain features (“The nanowire stack 222 is formed over the P well 2002 and forms the channel regions of the first pass-gate node 202 and the first pull-down node 210” ¶ [0025]; ), the first source/drain features interfaces the second source/drain features (“As shown in FIG. 2B, line B-B′ passes through the source/drain regions 250 and channel regions 255 of the first pass-gate node 202 and the first pull-down node 210.” ¶ [0029]) and a metal feature landing on where the first source/drain features interface the second source/drain features (“The source/drain regions 250 may be electrically coupled to source/drain contacts 270 via silicide layers 260.” ¶ [0030]).
Furthermore, In the similar field of endeavor of semiconductor devices, KWON et al. Figs. 1-2, discloses the first pass transistor 303 and the first inverter 351 may share the first drain pattern 41 as a common drain terminal, thereby reducing the area of the semiconductor device 1 (¶ [0041]), The output terminal of the first inverter 351 may be connected to the second drain pattern 42 through a first node contact 101. The output terminal of the second inverter 352 may be connected to the first drain pattern 41 through a second node contact 102 (¶ [0044]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the first SRAM cell of Patent-387 with the teaching the first source/drain the second source/drain features, the first source/drain features interfaces the second source/drain features and a metal feature landing on where the first source/drain features interface the second source/drain features of Liaw and KWON et al. in order to reduce the area of the semiconductor device (KWON et al. ¶ [0041]).
Claim 14 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13-14 and claims 1 and 11, respectively of US 12127387 B2 “Patent-387”.
Claim limitations of Instant Application
Claim limitations of US 12127387 B2
Claim 14,
The semiconductor structure of claim 12,
wherein a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5,
wherein a ratio of the fourth channel width to the second channel width is in a range of 1.2 to 5,
wherein a ratio of the sixth channel width to the third channel width is in a range of 1.05 to 1.5.
Claim 13,
A semiconductor structure, comprising:
a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5,
(claim 13) a ratio of the fifth channel width to the second channel width is in a range of 1.2 to 5, (Claim 14) wherein the fourth and the fifth channel widths are substantially same.
a ratio of the sixth channel width to the third channel width is in a range of 1.05 to 1.5
Claim 20, The semiconductor structure of claim 1,
wherein a ratio of the fourth channel width to the sixth channel width is in a range of 1.5 to 5.
Claim 11, The semiconductor structure of claim 1,
wherein each of the third and the fourth pull-up GAA transistors has a sixth channel width, and a ratio of the third channel width to the sixth channel width is in a range of 1.5 to 5.
(this is from claim 1 G) each of the third and the fourth pass-gate GAA transistors has a third channel width, each of the third and the fourth pull-down GAA transistors has a fourth channel width, and the third and the fourth channel widths are substantially same, and
Regarding Claim 14, Patent-387 claim 13 and 14 recites a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5; and a ratio of the sixth channel width to the third channel width is in a range of 1.05 to 1.5. Instant claim 14 recites a ratio of the fourth channel width to the second channel width is in a range of 1.2 to 5, Patent-387 claim 13 recites a ratio of the third channel width to the sixth channel width is in a range of 1.5 to 5 and Patent-387 claim 14 recited fourth and fifth channel widths are same. Therefore, the fourth/second ratio claimed in the Patent-387 substantially coincides with and at least overlaps, the instant claim range.
Regarding Claim 20, Patent-387 claim 11 recites a third channel width/sixth channel width ratio of 1.5 to 5; Patent-387 claim 1 recites the third and the fourth channel widths are substantially same. Therefore, the fourth/sixth channel widths ratio claimed in the Patent-387 substantially coincides with and at least overlaps, the instant claim range of 1.5 to 5.
Allowable Subject Matter
Claims 1-20 would be allowable upon resolving the 35 U.S.C. 112(b), 35 U.S.C. 112(a) and Nonstatutory Double patenting rejections.
The reason for allowance of claims 1 is the prior art of record, (US 20200135740 A1) “Liaw”, Yang, Haining (US 20210020643 A1) “Yang”, (US 20160104524 A1) “Liaw-1”, KWON; DAE-JIN (US 20170148505 A1) “KWON et al.” and HUNT-SCHROEDER, Eric (US 20170270999 A1) “HUNT-SCHROEDER et al.” alone or in combination, does not teach or fairly suggest, the sixth channel width is greater than the fifth channel width, in combination with other limitations of claim 1.
Claims 2-11 and 19-20 are indicated allowable, based on their dependency on claim 1.
The reason for allowance of claims 12 are the prior art of record, (US 20200135740 A1) “Liaw”, Yang, Haining (US 20210020643 A1) “Yang”, (US 20160104524 A1) “Liaw-1”, KWON; DAE-JIN (US 20170148505 A1) “KWON et al.” and HUNT-SCHROEDER, Eric (US 20170270999 A1) “HUNT-SCHROEDER et al.” alone or in combination, does not teach or fairly suggest, wherein the sixth channel width is greater than the third channel width, in combination with other limitations of claim 12.
Claims 13-17 are indicated allowable, based on their dependency on claim 12.
The reason for allowance of claims 18 are the prior art of record, (US 20200135740 A1) “Liaw”, Yang, Haining (US 20210020643 A1) “Yang”, (US 20160104524 A1) “Liaw-1”, KWON; DAE-JIN (US 20170148505 A1) “KWON et al.” and HUNT-SCHROEDER, Eric (US 20170270999 A1) “HUNT-SCHROEDER et al.” alone or in combination, does not teach or fairly suggest, wherein the sixth channel width is greater than the third channel width, in combination with other limitations of claim 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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