Prosecution Insights
Last updated: October 01, 2026
Application No. 18/782,439

HIGH ASPECT RATIO BOSCH DEEP ETCH

Non-Final OA §102§DP
Filed
Jul 24, 2024
Priority
Sep 25, 2020 — divisional of 11/361,971 +1 more
Examiner
CHAMBLISS, ALONZO
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
66%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
1086 granted / 1206 resolved
+30.0% vs TC avg
Minimal -24% lift
Without
With
+-24.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
28 currently pending
Career history
1213
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
35.8%
-4.2% vs TC avg
§102
31.8%
-8.2% vs TC avg
§112
15.2%
-24.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1206 resolved cases

Office Action

§102 §DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The preliminary amendment filed on 2/28/2025 has been fully considered and made of record in this application. Information Disclosure Statement The information disclosure statement (IDS) submitted on 7/24/2024, 1/16/2025, 5/14/2025, and 7/14/2025 was filed after the mailing date of the Non-final rejection on 9/19/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The formal drawings filed on 7/24/2024 have been approved by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 21-23, 27, and 28 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Yen et al. (US 2017/0186837). With respect to Claim 21, Yen teaches a semiconductor substrate 102 including a trench 104 extending downward into an upper surface of the semiconductor substrate. The trench 104 having a depth and including a bottom surface and a plurality of scallops along sidewalls of the trench. An oxide layer 304 lining the bottom surface and the sidewalls of the trench, wherein the oxide layer 304 has varying thicknesses along the sidewalls of the trench at different depths. A first conductive layer 306 disposed along inner sidewalls of the oxide layer and disposed over a base portion of the oxide layer 304. The first conductive layer 306 has a substantially constant thickness along the sidewalls throughout the depth of the trench (see paragraphs 16-53; Figs 3, 4A-4C, 7, 12, and 13). With respect to Claim 22, Yen teaches the varying thicknesses of the oxide layer 304 include a first thickness that remains constant over multiple upper scallops at a first range of depths on the sidewalls of the trench. Then changes to a second thickness that remains constant over multiple middle scallops at a second range of depths on the sidewalls of the trench (see Figs. 3, 4A-4C, 7, 12, and 13). With respect to Claim 23, Yen teaches the varying thicknesses of the oxide layer 304 include a third thickness that remains constant over multiple lower scallops at a third range of depths on the sidewalls of the trench 104, the first thickness being greater than the second thickness, and the second thickness being greater than the third thickness (see Figs. 3, 4A-4C, 7, 12, and 13). With respect to Claim 27, Yen teaches the base portion of the oxide layer 304 has a substantially constant thickness from a first sidewall of the trench 104 to a second sidewall of the trench. The second sidewall of the trench being opposite the first sidewall of the trench (see Figs. 3, 4A-4C, 7, 12, and 13). With respect to Claim 28, Yen teaches the first conductive layer 306 has a substantially constant thickness over the base portion of the oxide layer from a first inner sidewall of the oxide layer to a second inner sidewall of the oxide layer(see Figs. 3, 4A-4C, 7, 12, and 13). Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 21-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. 12,406,851. Although the claims at issue are not identical, they are not patentably distinct from each other because both the application and the patent recite a semiconductor substrate including a trench extending downward into an upper surface of the semiconductor substrate. The trench having a depth and including a bottom surface and a plurality of scallops along sidewalls of the trench. An oxide layer lining the bottom surface and the sidewalls of the trench, wherein the oxide layer has varying thicknesses along the sidewalls of the trench at different depths. A first conductive layer disposed along inner sidewalls of the oxide layer and disposed over a base portion of the oxide layer. The first conductive layer has a substantially constant thickness along the sidewalls throughout the depth of the trench. Claims 21-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of U.S. Patent No. 12,406,851. Although the claims at issue are not identical, they are not patentably distinct from each other because both the application and the patent recite a semiconductor substrate including a trench extending downward into an upper surface of the semiconductor substrate. The trench including a bottom surface and a plurality of scallops along sidewalls of the trench. An oxide layer lining the bottom surface and the sidewalls of the trench. A first conductive layer disposed along inner sidewalls of the oxide layer and disposed over a base portion of the oxide layer. The uppermost sidewall regions of the oxide layer in the trench have a first thickness, middle sidewall regions of the oxide layer in the trench have a second thickness, and lowermost sidewall regions in the trench have a third thickness. The first thickness is greater than the second thickness, and the second thickness is greater than the third thickness. The first conductive layer has a substantially constant thickness along the sidewalls throughout a depth of the trench. Allowable Subject Matter Claims 38-40 are allowed. Claims 24-26, 29-37 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowance subject matter: none of the prior art of record teaches or suggest the combination of a first difference between the first thickness and the second thickness is less than a second difference between the second thickness and the third thickness in claim 24. A first difference between the first thickness and the second thickness is equal to a second difference between the second thickness and the third thickness in claim 25. An insulating layer disposed along inner sidewalls of the first conductive layer and disposed over a base portion of the first conductive layer. A second conductive layer disposed along inner sidewalls of the insulating layer and disposed over a base portion of the insulating layer in claim 29. The uppermost sidewall regions of the oxide layer in the trench have a first thickness, middle sidewall regions of the oxide layer in the trench have a second thickness, and lowermost sidewall regions in the trench have a third thickness. The first thickness is greater than the second thickness, and the second thickness is greater than the third thickness. The first conductive layer has a substantially constant thickness along the sidewalls throughout a depth of the trench in claim 30. A first conductive layer disposed along inner sidewalls of the dielectric layer. A first thickness difference is defined between and the first thickness of the dielectric layer and a first thickness of the first conductive layer at the first trench depth. A second thickness difference is defined between and the second thickness of the dielectric layer and a second thickness of the first conductive layer at the second trench depth. The first thickness difference is greater than the second thickness difference in claim 38. Conclusion 12. Any inquiry concerning the communication or earlier communications from the examiner should be directed to Alonzo Chambliss whose telephone number is (571) 272-1927. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system Status information for published applications may be obtained from either Private PMR or Public PMR. Status information for unpublished applications is available through Private PMR only. For more information about the PMR system see hittp://pair-dkect.usptol gov. Should you have questions on access to the Private PMR system contact the Electronic Center (EBC) at 866-217-9197 (toll-free). AC/September 19, 2026 /Alonzo Chambliss/ Primary Examiner, Art Unit 2897
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Prosecution Timeline

Jul 24, 2024
Application Filed
Feb 28, 2025
Response after Non-Final Action
Sep 23, 2026
Non-Final Rejection mailed — §102, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
66%
With Interview (-24.2%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1206 resolved cases by this examiner. Grant probability derived from career allowance rate.

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