DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/23/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-20 of U.S. Patent No. 12,237,397 (“Wang”). Although the claims at issue are not identical, they are not patentably distinct from each other because the difference in claim language largely amounts to a rewording of already protected embodiments found in the cited reference. Below, the pending claims are compared to the patented claim limitations. The patented claim language is italicized.
Pending Claim 1 recites a method of forming a semiconductor device, the method comprising:
forming on a substrate a fin protruding above a top surface of an isolation layer, the fin having a longitudinal axis extending in a first direction;
depositing over the fin and the isolation layer a dummy gate dielectric layer and a dummy gate electrode layer;
Patented Claim 18 recites a method of forming a device, the method comprising:
forming over a fin structure a polysilicon layer, the fin structure having a longitudinal axis in a first direction;
patterning the dummy gate electrode layer to form a dummy gate electrode extending over the fin and having a longitudinal axis extending in a second direction perpendicular to the first direction, wherein the patterning results in the dummy gate electrode having a core portion with a constant width in the first direction and a footer portion that extends outwards from the core portion, the footer portion being along an interface of the dummy gate electrode and the isolation layer;
etching the polysilicon layer to form a dummy gate, wherein the dummy gate has an upper portion with a nominal width, measured in the first direction, and the dummy gate further has a lower portion that flares out to a second width, measured in the first direction, wider than the nominal width;
depositing a dielectric layer over the dummy gate electrode and the isolation layer;
removing the core portion of the dummy gate electrode while leaving the footer portion of the dummy gate electrode intact to form a trench in the dielectric layer wherein the trench is lined with the footer portion of the dummy gate electrode along a bottom corner of the trench; and
forming an insulating material around the dummy gate;
removing the upper portion of the dummy gate to form a trench in the insulating material while leaving the lower portion of the dummy gate in place; and
forming a metal gate structure in the trench.
forming over the lower portion of the dummy gate a metal gate electrode.
The pending claim differs from the patented claim largely by rewording the already protected claim language. The patented claim language requires the dummy gate and subsequent footer portion be formed from polysilicon but the removal of this limitation does not provide for a patentable distinction since the use of known materials amounts to an obvious modification.
For brevity, the dependent claims are matched to their equivalent in the cited patent without repetition of claim language.
Pending Claim 2 is obvious in view of patented Claim 18.
Pending Claim 3 is obvious in view of patented Claim 18.
Pending Claim 4 is unpatentable in view of patented Claim 1.
Pending Claim 5 is obvious in view of patented Claim 12.
Pending Claim 6 is obvious in view of patented Claim 13.
Pending Claim 7 is obvious in view of patented Claims 14 & 15.
Pending Claim 8 is obvious in view of patented Claim 9.
Patented Claim 9 recites a method of forming a semiconductor device, the method comprising:
depositing a polysilicon layer over a fin;
Pending Claim 18 recites a method of forming a device, the method comprising:
forming over a fin structure a polysilicon layer, the fin structure having a longitudinal axis in a first direction;
etching the polysilicon layer to form a dummy gate structure to have a nominal periphery with a desired top down view shape, wherein the dummy gate structure includes a desires region having the nominal periphery and a footer region that extends laterally outside the nominal periphery;
etching the polysilicon layer to form a dummy gate, wherein the dummy gate has an upper portion with a nominal width, measured in the first direction, and the dummy gate further has a lower portion that flares out to a second width, measured in the first direction, wider than the nominal width;
depositing a dielectric layer over the fin and the dummy gate structure;
removing the desired region of the dummy gate electrode while leaving the footer region of the dummy gate structure intact; and
forming an insulating material around the dummy gate;
removing the upper portion of the dummy gate to form a trench in the insulating material while leaving the lower portion of the dummy gate in place; and
filling a void left by the removed desired portion of the dummy gate structure with a metal gate structure, wherein the footer region of the dummy gate electrode is interposed between the metal gate structure and adjacent structures.
forming over the lower portion of the dummy gate a metal gate electrode.
The pending claim differs from the patented claim largely by rewording the already protected claim language. The pending claim requires “the footer region of the dummy gate electrode is interposed between the metal gate structure and adjacent structures”. However, the limitation is an obvious result of the method since the footer regions are adjacent to the metal gate structure and therefore between the metal gate structure and adjacent structures.
For brevity, the dependent claims are matched to their equivalent in the cited patent without repetition of claim language.
Pending Claim 10 is obvious in view of patented Claim 18.
Pending Claim 11 is obvious in view of patented Claim 18.
Pending Claim 12 is obvious in view of patented Claim 9.
Pending Claim 13 is obvious in view of patented Claim 1.
Pending Claim 14 is obvious in view of patented Claims 1 & 18.
Pending Claim 15 is obvious in view of patented Claims 16 & 18.
Pending Claim 16 is obvious in view of patented Claim 19.
Pending Claim 17 recites a device comprising:
an isolation layer on a substrate;
a fin extending above a top surface of the isolation layer, the fin extending in a first direction;
Patented Claim 1 recites a device comprising:
a fin extending upwards from a substrate;
an isolation material at least partially surrounding the fin;
a metal gate structure extending over the isolation layer and over the fin in a second direction perpendicular to the first direction;
a dielectric gate spacer extending up a sidewall of the metal gate structure; and
a metal gate electrode and gate dielectric extending over a top and sidewalls of the fin; and
a polysilicon remnant material interjacent the metal gate structure and the dielectric gate spacer at a lower portion of the sidewall of the metal gate structure, the dielectric gate spacer contacting the sidewall of the metal gate structure at an upper portion of the sidewall.
a polysilicon material extending along respective bottom portions of sidewalls of the metal gate electrode, the polysilicon material being interjacent the gate dielectric and the substrate in a direction perpendicular to the major surface of the substrate.
The pending claim differs from the patented claim largely by rewording the already protected claim language. The pending claim additionally requires a dielectric gate spacer extending up a sidewall of the metal gate structure. However, gate spacers were known at the time of the invention to enhance electrical isolation for the gate electrode and prevent parasitic capacitance.
For brevity, the dependent claims are matched to their equivalent in the cited patent without repetition of claim language.
Pending Claim 18 is obvious in view of patented Claims 12 & 13.
Pending Claim 19 is obvious in view of patented Claim 1.
Pending Claim 20 is obvious in view of patented Claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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