Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of claims 1, 10, 17, “a first portion of the metal gate stack disposed between a first semiconductor layer and a second semiconductor layer of the stack has a first length, wherein a second portion of the metal gate stack disposed between the second semiconductor layer and a third semiconductor layer of the stack has a second length, and wherein the first length is greater than the second length” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. The claimed device, which appears to be Figs. 18A/18B, does not show two gate portions with different lengths, each gate portion between two layers of a semiconductor stack. The gate portion with a greater length, that is Fig. 18B 262c, appears to be placed directly on the substrate without a semiconductor layer below it.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2, 18 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The limitations regarding the first semiconductor layer(s) directly contacting the substrate does not appear in the specification. Paragraph 0015 of the specification of the application at hand does not provide the requisite detail to justify the limitations recited in claims 2 and 18, nor do the present drawings feature the claimed invention as possessing such a feature.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 7, 9-13, 16-17, 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al.(US 20190196830 A1, hereafter Lilak).
Regarding Claim 1, Lilak discloses:
A semiconductor structure(Fig. 20B), comprising:
a substrate(Fig. 20B [102]);
a stack of semiconductor layers(Fig. 20B [106-1/106-2]) disposed over the substrate(Fig. 20B [102]);
source/drain(S/D) features(Fig. 20B [118-1/118-2]) adjacent to and interfacing each semiconductor layer(Fig. 20B [106-1/106-2]) of the stack of semiconductor layers(Fig. 20B [106-1/106-2]); and
a metal gate stack(Fig. 20B [124-1/124-2]) interleaved with the stack of semiconductor layers(Fig. 20B [106-1/106-2]), wherein a first portion(Fig. 20B [124-1]) of the metal gate stack(Fig. 20B [124-1/124-2]) disposed between a first semiconductor layer(Fig. 20B See figure below) and a second semiconductor layer(Fig. 20B See figure below) of the stack(Fig. 20B [106-1/106-2]) has a first length, wherein a second portion(Fig. 20B [124-2]) of the metal gate stack(Fig. 20B [124-1/124-2]) disposed between a second semiconductor layer(Fig. 20B See figure below) and a third semiconductor layer(Fig. 20B See figure below) of the stack(Fig. 20B [106-1/106-2]) has a second length, and wherein the first length is greater than the second length.
Regarding Claim 3, Lilak further discloses:
The stack(Fig. 20B [106-1/106-2]) is a first stack, the semiconductor structure(Fig. 20B) further comprising second stack of semiconductor layers(Fig. 20B See figure below) disposed over the substrate(Fig. 20B [102]), wherein the metal gate stack(Fig. 20B [124-1/124-2]) is interleaved with the second stack(Fig. 20B See figure below), and wherein portions of the metal gate stack(Fig. 20B [124-1/124-2]) disposed between the semiconductor layers(Fig. 20B See figure below) of the second stack(Fig. 20B See figure below) have the same length(See each of 124-1 or 124-2).
Regarding Claim 4, Lilak further discloses:
Portions of the metal gate stack(Fig. 20B [124-1/124-2]) interleaved with the second stack(Fig. 20B See figure below) have a third length, and wherein the third length is the same as the second length.
While not explicitly stated by Lilak, one of ordinary skill in the art would take identically presented features of the sub-stacks 124-1 or 124-2 as being of the same length between stacks.
Regarding Claim 7, Lilak further discloses:
A source/drain(S/D) feature(Fig. 20B [118-1/118-2]) disposed in the stack(Fig. 20B [106-1/106-2]) and adjacent to the metal gate stack(Fig. 20B [124-1/124-2]);
First inner spacers(Fig. 20B See figure below) between the S/D feature(Fig. 20B [118-1/118-2]) and the first portion(Fig. 20B [124-1]) of the metal gate stack(Fig. 20B [124-1/124-2]), wherein the first inner spacers(Fig. 20B See figure below) have a first thickness; and
Second inner spacers(Fig. 20B See figure below) between the S/D feature(Fig. 20B [118-1/118-2]) and the second portion(Fig. 20B [124-2]) of the metal gate stack(Fig. 20B [124-1/124-2]), wherein the second inner spacers(Fig. 20B See figure below) have a second thickness, wherein the first thickness is less than the second thickness.
Regarding Claim 9, Lilak further discloses:
The S/D feature(Fig. 20B [118-1/118-2]) extends below bottom surfaces of the first inner spacers(Fig. 20B See figure below).
Regarding Claim 10, Lilak discloses:
A semiconductor structure(Fig. 20B), comprising:
A substrate(Fig. 20B [102]);
A stack of semiconductor layers(Fig. 20B [106-1/106-2]) disposed over the substrate(Fig. 20B [102]); and
a metal gate stack(Fig. 20B [124-1/124-2]) interleaved with the stack of semiconductor layers(Fig. 20B [106-1/106-2]), wherein a first portion(Fig. 20B [124-1]) of the metal gate stack(Fig. 20B [124-1/124-2]) disposed between a first semiconductor layer(Fig. 20B See figure below) and a second semiconductor layer(Fig. 20B See figure below) of the stack(Fig. 20B [106-1/106-2]) has a first uniform gate length, wherein a second portion(Fig. 20B [124-2]) of the metal gate stack(Fig. 20B [124-1/124-2]) disposed between the second semiconductor layer(Fig. 20B See figure below) and a third semiconductor layer(Fig. 20B See figure below) of the stack(Fig. 20B [106-1/106-2]) has a second uniform gate length, and wherein the first uniform gate length is greater than the second uniform gate length.
Regarding Claim 11, Lilak further discloses:
Source/drain(S/D) features(Fig. 20B [118-1/118-2]) adjacent to and interfacing each semiconductor layer(Fig. 20B [106-1/106-2]) of the stack of semiconductor layers(Fig. 20B [106-1/106-2]).
Regarding Claim 12, Lilak further discloses:
The stack(Fig. 20B [106-1/106-2]) is a first stack, the semiconductor structure(Fig. 20B) further comprising second stack of semiconductor layers(Fig. 20B See figure below) disposed over the substrate(Fig. 20B [102]), wherein the metal gate stack(Fig. 20B [124-1/124-2]) is interleaved with the second stack(Fig. 20B See figure below), and wherein portions of the metal gate stack(Fig. 20B [124-1/124-2]) disposed between the semiconductor layers(Fig. 20B See figure below) of the second stack(Fig. 20B See figure below) have a same uniform gate length(See each of 124-1 or 124-2).
Regarding Claim 13, Lilak further discloses:
The same uniform gate length of the portions of the metal gate stack(Fig. 20B [124-1/124-2]) interleaved with the second stack(Fig. 20B See figure below) is the same as the second uniform gate length.
Regarding Claim 16, Lilak further discloses:
The first semiconductor layer(Fig. 20B See figure below) is a bottommost semiconductor layer of the stack(Fig. 20B [106-1/106-2]), and the first portion(Fig. 20B [124-1]) of the metal gate stack(Fig. 20B [124-1/124-2]) directly interfaces a top surface of the first semiconductor layer(Fig. 20B See figure below) and a bottom surface of the second semiconductor layer(Fig. 20B See figure below) at the first uniform gate length.
Regarding Claim 17, Lilak discloses:
A semiconductor structure(Fig. 20B), comprising:
A substrate(Fig. 20B [102]);
A first stack(Fig. 20B See figure below) and a second stack(Fig. 20B See figure below) of semiconductor layers disposed over the substrate(Fig. 20B [102]);
First source/drain(S/D) features(Fig. 20B [118-1/118-2]) adjacent to and interfacing each semiconductor layer(Fig. 20B [106-1/106-2]) of the first stack(Fig. 20B See figure below) of semiconductor layers;
Second source/drain(S/D) features(Fig. 20B [118-1/118-2]) adjacent to and interfacing each semiconductor layer(Fig. 20B [106-1/106-2]) of the second stack(Fig. 20B See figure below) of semiconductor layers;
A metal gate stack(Fig. 20B [124-1/124-2]) interleaved with the first stack of semiconductor layers(Fig. 20B See figure below) and the second stack of semiconductor layers(Fig. 20B See figure below),
Wherein a first portion(Fig. 20B [124-1]) of the metal gate stack(Fig. 20B [124-1/124-2]) disposed between a first semiconductor layer(Fig. 20B See figure below) and a second semiconductor layer(Fig. 20B See figure below) of the first stack(Fig. 20B See figure below) has a first length, wherein a second portion(Fig. 20B [124-2]) of the metal gate stack(Fig. 20B [124-1/124-2]) disposed between a second semiconductor layer(Fig. 20B See figure below) and a third semiconductor layer(Fig. 20B See figure below) of the first stack(Fig. 20B See figure below) has a second length, and wherein the first length is greater than the second length,
Wherein a third portion(Fig. 20B See figure below) of the metal gate stack(Fig. 20B [124-1/124-2]) disposed between a first semiconductor layer(Fig. 20B See figure below) and a second semiconductor layer(Fig. 20B See figure below) of the second stack(Fig. 20B See figure below) has a third length, and wherein a fourth portion of the metal gate stack(Fig. 20B [124-1/124-2]) disposed between the second semiconductor layer(Fig. 20B See figure below) and a third semiconductor layer(Fig. 20B See figure below) of the second stack(Fig. 20B See figure below) has a fourth length, and wherein the third length has a same length as the fourth length.
Regarding Claim 19, Lilak further discloses:
The second length and the third length have the same length.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6, 8, 14-15, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lilak.
Regarding Claim 5,
Lilak discloses that their transistor may form a part of an SRAM device(See Paragraph 0052).
It would have been obvious to one of ordinary skill in the art at the time the application at hand to arrive at the limitations of claim 5 from the teaching of Lilak. Pass-gate and pull-down(PG and PD) transistors are known elements of an SRAM transistor cell, and with the teaching of Lilak that the provided device can perform as elements of an SRAM device, one of ordinary skill in the art would naturally understand the usefulness of Lilak’s provided transistors towards that purpose. Producing such a device would have generated a predictable result in an SRAM cell utilizing Lilak’s transistors as elements within the cell.
Regarding Claim 6,
Lilak discloses that a difference in length between the first and second gates should be greater than 3 nanometers(See paragraph 0190).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitation based on the teaching of Lilak. Producing a device in accordance with the teachings of Lilak on the lower end of Lilak’s provided range would produce a device in accordance with the limitations of claim 6. Therefore, the limitation could have been arrived at via routine experimentation, producing a predictable result in an embodiment of Lilak’s device.
Regarding Claim 8,
Lilak discloses that a difference in length between the first and second gates should be greater than 3 nanometers(See paragraph 0190). Since each gate plus two spacers generates an equivalent width due to the vertical orientation of the semiconductor and gate stacks, one of ordinary skill in the art can take away the inference that a spacer is going to have half of the difference in width as the total difference in gate widths(Due to Gate 1 + 2 Spacer 1 = Gate 2 + 2 Spacer 2), implying a difference in spacer thickness of more than 1.5 nanometers.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitation based on the teaching of Lilak. Producing a device in accordance with the teachings of Lilak on the lower end of Lilak’s provided range would produce a device in accordance with the limitations of claim 8. Therefore, the limitation could have been arrived at via routine experimentation, producing a predictable result in an embodiment of Lilak’s device.
Regarding Claim 14,
Lilak discloses that a difference in uniform length between the first and second gates should be greater than 3 nanometers(See paragraph 0190).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitation based on the teaching of Lilak. Producing a device in accordance with the teachings of Lilak on the lower end of Lilak’s provided range would produce a device in accordance with the limitations of claim 14. Therefore, the limitation could have been arrived at via routine experimentation, producing a predictable result in an embodiment of Lilak’s device.
Regarding Claim 15,
Lilak discloses that their transistor may form a part of an SRAM device(See Paragraph 0052).
It would have been obvious to one of ordinary skill in the art at the time the application at hand to arrive at the limitations of claim 5 from the teaching of Lilak. Pass-gate(PD) transistors are known elements of an SRAM transistor cell, and with the teaching of Lilak that the provided device can perform as elements of an SRAM device, one of ordinary skill in the art would naturally understand the usefulness of Lilak’s provided transistors towards that purpose. Producing such a device would have generated a predictable result in an SRAM cell utilizing Lilak’s transistors as elements within the cell.
Lilak discloses that their transistor may form a part of an SRAM device(See Paragraph 0052).
It would have been obvious to one of ordinary skill in the art at the time the application at hand to arrive at the limitations of claim 5 from the teaching of Lilak. Pass-gate and pull-down(PG and PD) transistors are known elements of an SRAM transistor cell, and with the teaching of Lilak that the provided device can perform as elements of an SRAM device, one of ordinary skill in the art would naturally understand the usefulness of Lilak’s provided transistors towards that purpose. Producing such a device would have generated a predictable result in an SRAM cell utilizing Lilak’s transistors as elements within the cell.
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Above: Fig. 20B of Lilak with relevant portions denoted by examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Merchant et al.(US 20220301936 A1) discloses a multi-gate length nanosheet transistor. Hook et al.(US 20190280113 A1) discloses a multi-gate length nanosheet transistor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897
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