DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “Method of Forming Semiconductor Memory Device With Gate Structure in Trench of Alternating Active and Insulating Layers”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims (10+16), (10+16+1), (10+16+1), (10+16+1), (10+16+1), (10+16+20), (10+16+20), (10+16), (10+16+11), (10+16), (10+16+19), (10+16+19+1), (10+16+19+17), (10+16+19), (10+16+19), (10+16+19+3), 16, 16, (16+1) and (16+1), respectively, of U.S. Patent No. 11,081,493 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because all pertinent limitations in the current claims are disclosed in the corresponding claims of U.S. Patent No. 11,081,493 B2; accordingly, one of ordinary skill in the art would have deemed the invention in current claims 1-20 to be an obvious variant of the invention in the corresponding claims of U.S. Patent No. 11,081,493 B2. A detailed mapping of the current claims to the claims of U.S. Patent No. 11,081,493 B2 is provided hereinafter.
Claims of current application (18/782,660)
Claims of U.S. Patent No. 11,081,493 B2
1. A method for forming a semiconductor device structure, comprising: forming a stack of alternatingly stacking active layers and insulating layers over an interconnect structure; etching the stack to form a trench; forming a gate structure in the trench; and etching the gate structure to form openings, wherein the gate structure is cut into plurality of gate lines which are physically and electrically isolated from each other.
Note: Although the claims of U.S. Patent No. 11,081,493 does not explicitly disclose the plurality of gate lines are physically and electrically isolated from each other, this limitation is deemed obvious because the first gate structure is cut to form a plurality of first gate lines, i.e., forming a plurality of lines from one structure readily provides a plurality of lines that are physically and electrically isolated.
10. A method for forming a semiconductor memory device, comprising: forming an interconnect structure over a substrate, the interconnect structure including an access line in a dielectric layer; forming a sacrificial via in the dielectric layer and on the access line; and forming a memory cell array over the interconnect structure, comprising: forming a stack of layers over the dielectric layer, the stack of layers including active layers interposed by an insulating layer; cutting the stack of layers to form first source/drain features and second source/drain features spaced apart from the first source/drain features by a trench; etching the sacrificial via through the trench to form a via hole exposing the access line; and depositing a conductive material in the trench and the via hole.
16. A method for forming a semiconductor memory device, comprising: forming a plurality of sacrificial vias in a dielectric layer; forming a stack of layers over the dielectric layer; etching the stack of layers to form a first trench, wherein the first trench overlaps the plurality of sacrificial vias; etching the plurality of sacrificial vias to form a plurality of via holes; filling the plurality of via holes and the first trench with a conductive material to form a plurality of first conductive vias and a first gate structure, respectively; and cutting the first gate structure to form a plurality of first gate lines corresponding to the plurality of first conductive vias.
2. The method for forming the semiconductor memory device as claimed in claim 1, further comprising: laterally recessing the insulating layers of the stack from the trench; and forming channel features on the insulating layers of the stack.
1. A method for forming a semiconductor memory device, comprising: forming a sacrificial via in a dielectric layer over a substrate; forming a first active layer over the dielectric layer; forming an insulating layer over the first active layer; forming a second active layer over the insulating layer; forming a trench through the second active layer, the insulating layer and the first active layer and corresponding to the sacrificial via; laterally etching the insulating layer from the trench to form a recess; forming a channel feature in the recess; removing the sacrificial via to form a via hole in the dielectric layer; and filling the trench and the via hole with a conductive material.
3. The method for forming the semiconductor memory device as claimed in claim 1, further comprising: forming a storage layer along the trench, wherein the gate structure is formed over the storage layer.
4. The method for forming the semiconductor memory device as claimed in claim 3, further comprising: forming a spacer layer on the storage layer, wherein the gate structure is formed over the storage layer.
3. The method for forming the semiconductor memory device as claimed in claim 1, further comprising, before removing the sacrificial via: forming a storage layer along a sidewall and a bottom surface of the trench; and forming a spacer layer on the storage layer.
5. The method for forming the semiconductor memory device as claimed in claim 3, wherein the storage layer includes a SiO.sub.2—SiN—SiO.sub.2 structure.
Although the claims of U.S. Patent No. 11,081,493 does not disclose a material for the storage layer, oxide-nitride-oxide storage (or charge trapping) layers were well-known and commonly used in the art.
6. The method for forming the semiconductor memory device as claimed in claim 1, wherein the interconnect structure includes a metal line, a dielectric layer over the metal line and a row of dielectric vias in the dielectric layer, and the trench overlaps the row of dielectric vias.
16. A method for forming a semiconductor memory device, comprising: forming a plurality of sacrificial vias in a dielectric layer; forming a stack of layers over the dielectric layer; etching the stack of layers to form a first trench, wherein the first trench overlaps the plurality of sacrificial vias; etching the plurality of sacrificial vias to form a plurality of via holes; filling the plurality of via holes and the first trench with a conductive material to form a plurality of first conductive vias and a first gate structure, respectively; and cutting the first gate structure to form a plurality of first gate lines corresponding to the plurality of first conductive vias.
20. The method for forming the semiconductor memory device as claimed in claim 16, further comprising: forming a metal line in the dielectric layer, wherein the sacrificial via is formed on the metal line.
7. The method for forming the semiconductor memory device as claimed in claim 6, further comprising, after etching the stack to form the trench: removing the row of dielectric vias to form a row of via holes; and forming a row of conductive vias in the row of via holes.
16. A method for forming a semiconductor memory device, comprising: forming a plurality of sacrificial vias in a dielectric layer; forming a stack of layers over the dielectric layer; etching the stack of layers to form a first trench, wherein the first trench overlaps the plurality of sacrificial vias; etching the plurality of sacrificial vias to form a plurality of via holes; filling the plurality of via holes and the first trench with a conductive material to form a plurality of first conductive vias and a first gate structure, respectively; and cutting the first gate structure to form a plurality of first gate lines corresponding to the plurality of first conductive vias.
8. The method for forming the semiconductor memory device as claimed in claim 1, further comprising: forming a dielectric layer over the stack; etching the dielectric layer to form a row of via holes, wherein the row of via holes overlaps the plurality of gate lines; and forming a row of conductive vias in the via holes.
16. A method for forming a semiconductor memory device, comprising: forming a plurality of sacrificial vias in a dielectric layer; forming a stack of layers over the dielectric layer; etching the stack of layers to form a first trench, wherein the first trench overlaps the plurality of sacrificial vias; etching the plurality of sacrificial vias to form a plurality of via holes; filling the plurality of via holes and the first trench with a conductive material to form a plurality of first conductive vias and a first gate structure, respectively; and cutting the first gate structure to form a plurality of first gate lines corresponding to the plurality of first conductive vias.
9. The method for forming the semiconductor memory device as claimed in claim 1, further comprising: depositing a dielectric layer to fill the openings.
11. The method for forming the semiconductor memory device as claimed in claim 10, wherein the sacrificial via is made of a dielectric material, and etching the sacrificial via comprises performing a wet etching process. (i.e., in order to acquire a dielectric, sacrificial via, dielectric would fill openings)
10. The method for forming the semiconductor memory device as claimed in claim 1, wherein a first active layer and a second active layer in the active layers of the stack are cut by the trench to form a first source/drain feature and a second source/drain feature of a memory transistor.
10. A method for forming a semiconductor memory device, comprising: forming an interconnect structure over a substrate, the interconnect structure including an access line in a dielectric layer; forming a sacrificial via in the dielectric layer and on the access line; and forming a memory cell array over the interconnect structure, comprising: forming a stack of layers over the dielectric layer, the stack of layers including active layers interposed by an insulating layer; cutting the stack of layers to form first source/drain features and second source/drain features spaced apart from the first source/drain features by a trench; etching the sacrificial via through the trench to form a via hole exposing the access line; and depositing a conductive material in the trench and the via hole.
11. A method for forming a semiconductor device structure, comprising: forming a stack of alternatingly stacking active layers and insulating layers over an interconnect structure; patterning the stack to form a first trench; forming channel features on side surfaces of the insulating layers exposed from the first trench; forming a storage layer to partially fill the first trench; and forming a first gate structure on the storage layer in the first trench.
10. A method for forming a semiconductor memory device, comprising: forming an interconnect structure over a substrate, the interconnect structure including an access line in a dielectric layer; forming a sacrificial via in the dielectric layer and on the access line; and forming a memory cell array over the interconnect structure, comprising: forming a stack of layers over the dielectric layer, the stack of layers including active layers interposed by an insulating layer; cutting the stack of layers to form first source/drain features and second source/drain features spaced apart from the first source/drain features by a trench; etching the sacrificial via through the trench to form a via hole exposing the access line; and depositing a conductive material in the trench and the via hole.
16. A method for forming a semiconductor memory device, comprising: forming a plurality of sacrificial vias in a dielectric layer; forming a stack of layers over the dielectric layer; etching the stack of layers to form a first trench, wherein the first trench overlaps the plurality of sacrificial vias; etching the plurality of sacrificial vias to form a plurality of via holes; filling the plurality of via holes and the first trench with a conductive material to form a plurality of first conductive vias and a first gate structure, respectively; and cutting the first gate structure to form a plurality of first gate lines corresponding to the plurality of first conductive vias.
19. The method for forming the semiconductor memory device as claimed in claim 18, further comprising, after etching the stack of layers to form the first trench: forming a channel feature on a sidewall of the first insulating layer between the first semiconductor layer and the second semiconductor layer; and forming a storage layer along a sidewall and a bottom surface of the first trench.
12. The method for forming the semiconductor memory device as claimed in claim 11, further comprising: forming a sacrificial via in a dielectric layer of the interconnect structure; removing the sacrificial via to form a via hole after patterning the stack to form the first trench; and forming a conductive via in the via hole.
1. A method for forming a semiconductor memory device, comprising: forming a sacrificial via in a dielectric layer over a substrate; forming a first active layer over the dielectric layer; forming an insulating layer over the first active layer; forming a second active layer over the insulating layer; forming a trench through the second active layer, the insulating layer and the first active layer and corresponding to the sacrificial via; laterally etching the insulating layer from the trench to form a recess; forming a channel feature in the recess; removing the sacrificial via to form a via hole in the dielectric layer; and filling the trench and the via hole with a conductive material.
13. The method for forming the semiconductor memory device as claimed in claim 11, further comprising: patterning the stack to form a second trench; forming a second gate structure in the second trench; and forming a conductive via on the second gate structure.
17. The method for forming the semiconductor memory device as claimed in claim 16, further comprising: etching the stack of layers to form a second trench; filling the second trench with the conductive material to form a second gate structure; cutting the second gate structure to form a plurality of second gate lines; and forming a plurality of second conductive vias over the plurality of second gate lines.
14. The method for forming the semiconductor memory device as claimed in claim 11, wherein the storage layer includes a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the oxide layer.
Although the claims of U.S. Patent No. 11,081,493 does not disclose a material for the storage layer, oxide-nitride-oxide storage (or charge trapping) layers were well-known and commonly used in the art.
15. The method for forming the semiconductor memory device as claimed in claim 11, further comprising: laterally recessing the insulating layers before forming the channel features on the side surfaces of the insulating layers.
1. A method for forming a semiconductor memory device, comprising: forming a sacrificial via in a dielectric layer over a substrate; forming a first active layer over the dielectric layer; forming an insulating layer over the first active layer; forming a second active layer over the insulating layer; forming a trench through the second active layer, the insulating layer and the first active layer and corresponding to the sacrificial via; laterally etching the insulating layer from the trench to form a recess; forming a channel feature in the recess; removing the sacrificial via to form a via hole in the dielectric layer; and filling the trench and the via hole with a conductive material.
16. The method for forming the semiconductor memory device as claimed in claim 11, further comprising: forming a spacer layer on the storage layer, wherein the gate structure is formed on the spacer layer, and the spacer layer is made of a conductive material.
3. The method for forming the semiconductor memory device as claimed in claim 1, further comprising, before removing the sacrificial via: forming a storage layer along a sidewall and a bottom surface of the trench; and forming a spacer layer on the storage layer.
17. A method for forming a semiconductor device structure, comprising: forming a plurality of sacrificial vias in a dielectric layer, wherein the sacrificial vias are arranged in a first direction with a first pitch; forming a stack of layers over the dielectric layer; etching the stack of layers to form a plurality of trenches, wherein the trenches are arranged in the first direction with a second pitch, and the first pitch is substantially twice the second pitch; etching the plurality of sacrificial vias to form a plurality of via holes; forming a plurality of first conductive vias in the plurality of via holes; and forming a plurality of gate structures in the plurality of trenches.
16. A method for forming a semiconductor memory device, comprising: forming a plurality of sacrificial vias in a dielectric layer; forming a stack of layers over the dielectric layer; etching the stack of layers to form a first trench, wherein the first trench overlaps the plurality of sacrificial vias; etching the plurality of sacrificial vias to form a plurality of via holes; filling the plurality of via holes and the first trench with a conductive material to form a plurality of first conductive vias and a first gate structure, respectively; and cutting the first gate structure to form a plurality of first gate lines corresponding to the plurality of first conductive vias.
18. The method for forming the semiconductor memory device as claimed in claim 17, wherein the trenches are divided into a first group of trenches overlapping the plurality of sacrificial vias and a second group of trenches staggering from the plurality of sacrificial vias.
16. A method for forming a semiconductor memory device, comprising: forming a plurality of sacrificial vias in a dielectric layer; forming a stack of layers over the dielectric layer; etching the stack of layers to form a first trench, wherein the first trench overlaps the plurality of sacrificial vias; etching the plurality of sacrificial vias to form a plurality of via holes; filling the plurality of via holes and the first trench with a conductive material to form a plurality of first conductive vias and a first gate structure, respectively; and cutting the first gate structure to form a plurality of first gate lines corresponding to the plurality of first conductive vias.
19. The method for forming the semiconductor memory device as claimed in claim 17, wherein the stack of layers includes a first active layer, a first insulating layer, a second active layer, and a second insulating layer sequentially stacked.
1. A method for forming a semiconductor memory device, comprising: forming a sacrificial via in a dielectric layer over a substrate; forming a first active layer over the dielectric layer; forming an insulating layer over the first active layer; forming a second active layer over the insulating layer; forming a trench through the second active layer, the insulating layer and the first active layer and corresponding to the sacrificial via; laterally etching the insulating layer from the trench to form a recess; forming a channel feature in the recess; removing the sacrificial via to form a via hole in the dielectric layer; and filling the trench and the via hole with a conductive material.
20. The method for forming the semiconductor memory device as claimed in claim 17, further comprising: laterally etching the first insulating layer to form a plurality of recesses after etching the stack of layers to form the plurality of trenches; and forming a plurality of channel features in the plurality of recesses.
1. A method for forming a semiconductor memory device, comprising: forming a sacrificial via in a dielectric layer over a substrate; forming a first active layer over the dielectric layer; forming an insulating layer over the first active layer; forming a second active layer over the insulating layer; forming a trench through the second active layer, the insulating layer and the first active layer and corresponding to the sacrificial via; laterally etching the insulating layer from the trench to form a recess; forming a channel feature in the recess; removing the sacrificial via to form a via hole in the dielectric layer; and filling the trench and the via hole with a conductive material.
Conclusion
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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