Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on 03/03/2022. It is noted, however, that applicant has not filed a certified copy of the 63/255,129 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 06/24/2026, 01/08/2026, 04/28/2025, 10/24/2024, and 07/24/2024 are being considered by the examiner.
Claim Objections
Claims 6, 15, and 20 are objected to because of the following informalities:
"fi" being a typographical error, to be corrected to "fin" .
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5, and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1).
Regarding claim 3, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 1.
Mochizuki et al. teaches removing (FIG.3) a portion of the first semiconductor layers (SiGe layers 105a-105d) to form a recess (recessed portion 130).
Mochizuki et al. does not teach forming an inner spacer in the recess; and forming the first dielectric liner layer adjacent to the inner spacer, wherein the first dielectric liner layer is in direct contact with the inner spacer.
However, Frougier et al. teaches forming an inner spacer (inner spacer 148) in the recess (FIG.5, recess 134); and
forming (FIG.14) the first dielectric liner layer (insulative coating 138) adjacent to the inner spacer (148), wherein the first dielectric liner layer is in direct contact (FIG.12) with the inner spacer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Frougier et al.’s dielectric liner, top semiconductor layer and s/d arrangement to Mochizuki’s et al.’s recessed s/d regions. Mochizuki et al. is interpreted such that in the single etch to form the s/d recess, the etch first forms the fin structure then continues to etch into the substrate to form the s/d recess. And the continuous etch will cause some amount of lateral etch to the fin structure. Both Mochizuki et al. and Frougier et al. are directed to fabrication of vertically stacked nanostructures with recessed s/d regions; thus, supplying the process steps and structures of Frougier et al. to that of Mochizuki et al. predictably enables region-specific effective nanosheet count, ultimately providing power-efficient and high-speed regions on the same chip. Frougier et al supplies selective dielectric liner adjacent to inner spacer, thus disabling lower nanostructures and defining which nanostructures remain active for optimal performance.
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FIG.13 of Frougier et al. (depicted above) does not explicitly label insulative coating 138 in highlights, although previously labeled in FIGS.10-12. Annotation above aims to, therefore, reinstate location of 138, mapped to as dielectric liner layers of claimed invention (e.g. FIG.3K-1).
Regarding claim 5, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 1. Mochizuki et al. teaches further comprising:
replacing (FIG.10) the dummy gate structure (dummy gate 110) with a first gate structure (gate region 180), wherein a top surface of the first top layer is higher than a bottommost surface of the first gate structure.
Regarding claim 7, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 1.
Frougier et al. teaches wherein a bottom surface of first S/D structure is higher than (FIG.14 and claim 9: positioned above) a bottom surface of the second S/D structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Frougier et al.’s dielectric liner, top semiconductor layer and s/d arrangement to Mochizuki’s et al.’s recessed s/d regions. Both Mochizuki et al. and Frougier et al. are directed to fabrication of vertically stacked nanostructures with recessed s/d regions; thus, supplying the process steps and structures of Frougier et al. to that of Mochizuki et al. predictably enables region-specific effective nanosheet count, ultimately providing power-efficient and high-speed regions on the same chip. Frougier et al. supplies layers at different heights in different regions, which enables different effective nanostructure counts for different performance targets in the same fin stack.
Regarding claim 8, Mochizuki et al. teaches a method for forming a semiconductor device structure, comprising:
forming a first fin structure (FIG.2, left nanostack) and a second fin structure (FIG.2, right nanostack) over a substrate (102),
wherein the first fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers (SiGe layers 105a-105d) stacked in a vertical direction (z-direction), and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers (Si layers 107a-107c) stacked in the vertical direction (FIG.2);
forming (FIG.2) a dummy gate structure (dummy gate 110) over the first fin structure and the second fin structure;
removing (FIG.2) a portion of the first fin structure and the second fin structure to form a first S/D recess (recessed portion 130) and a second S/D recess (recessed portion 130); and
removing (FIG.3) a portion of the second semiconductor layers (Si layers 107a-107c) to form a first recess (recessed portion 130) and a second recess (recessed portion 130);
Mochizuki et al. does not teach forming a first inner spacer and a second inner spacer adjacent to the first semiconductor layers; and forming a first dielectric liner layer in the first recess and a second dielectric liner layer in the second recess, wherein an outer sidewall surface of the first dielectric liner layer is aligned with an outer sidewall surface of the first inner spacer.
However, Frougier et al. teaches forming (FIG.14, regions 100L and 100S, respectively) a first inner spacer (inner spacer 148) and a second inner spacer (inner spacer 148) adjacent to ((42), laterally adjacent) the first semiconductor layers (sacrificial nanosheets 118); and
forming (FIG.10, regions 100L and 100S, respectively) a first dielectric liner layer (insulative coating 138) in the first recess (recess 114R) and a second dielectric liner layer (insulative coating 138) in the second recess (recess 114R),
wherein an outer sidewall surface (FIG.10, 12) of the first dielectric liner layer (insulative coating 138) is aligned with an outer sidewall surface of the first inner spacer (inner spacers 148).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Frougier et al.’s dielectric liner, top semiconductor layer and s/d arrangement to Mochizuki’s et al.’s recessed s/d regions. Both Mochizuki et al. and Frougier et al. are directed to fabrication of vertically stacked nanostructures with recessed s/d regions; thus, supplying the process steps and structures of Frougier et al. to that of Mochizuki et al. predictably enables region-specific effective nanosheet count, ultimately providing power-efficient and high-speed regions on the same chip. Frougier et al.’s arrangement of aligned inner spacer and dielectric liner defines which nanostructures remain active and provides known configuration for formation of s/d region of stacked device, further supporting incorporation to Mochizuki’s method of manufacturing.
Regarding claim 9, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 8. Mochizuki et al. teaches further comprising:
forming (FIG.6) a first bottom layer (lower epitaxial layer 160) in the first S/D recess (recessed portion 130) and a second bottom layer (lower epitaxial layer 160) in the second S/D recess (recessed portion 130).
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1) and Huang et al. (US 9793174 B1).
Regarding claim 2, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 1.
Huang et al. teaches further comprising: forming (FIG.9) a first insulating layer (patterned photoresist layer 351) over the first top layer (insulating layer 200) and a second insulating layer (insulating layer 250) over the second bottom layer (bottom oxide layer 303), wherein a top surface of the first insulating layer is higher (FIG.9) than a top surface of the second insulating layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include insulating layer arrangement of Huang et al. to the method of Mochizuki et al. as modified by Frougier et al. By forming insulating layers over different portions of device at varying vertical layers, Huang et al. provides a known technique for electrically isolating s/d region from lower layers. The asymmetry in heights of insulating layer is result from forming layers over device regions having different vertical structures and dimensions.
Regarding claim 12, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 11. Huang et al. teaches further comprising:
forming (FIG.9) a first insulating layer (patterned photoresist layer 351) over the first top layer (insulating layer 200).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have include insulating layer arrangement of Huang et al. to the method of Mochizuki et al. as modified by Frougier et al. By forming insulating layers over different portions of device at varying vertical layers, Huang et al. provides a known technique for electrically isolating s/d region from lower layers, such that some stacked nanostructures remain electrically active while others are blocked off for optimization of power versus speed.
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1) and Akarvardar et al. (US 8809947 B1).
Regarding claim 6, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 1. Akarvardar et al. teaches further comprising:
forming (FIG.6) a cladding layer (upper cladding layer 14 + side cladding layer 60) over a top surface and a sidewall surface of the first fin structure (non-planar transistor structure 20, leftside) and a top surface and a sidewall surface of the second fin structure (non-planar transistor structure 20, rightside).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the cladding layers of Akarvardar et al. to the structure of Mochizuki et al. as modified by Frougier et al. By forming cladding material over the top and sidewalls of non-planar semiconductor structure, Akarvardar et al. provides known protective layer over exposed surfaces and thus provides process for tuning transistor performance by region during fabrication.
Regarding claim 15, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 8. Akarvardar et al. teaches further comprising:
forming (FIG.6) a cladding layer (upper cladding layer 14 + side cladding layer 60) over a top surface and a sidewall surface of the first fin structure (non-planar transistor structure 20, leftside) and a top surface and a sidewall surface of the second fin structure (non-planar transistor structure 20, rightside).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the cladding layers of Akarvardar et al. to the structure of Mochizuki et al. as modified by Frougier et al. By forming cladding material over the top and sidewalls of non-planar semiconductor structure, Akarvardar et al. provides known protective layer over exposed surfaces and thus provides process for tuning transistor performance by region during fabrication.
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1) and Peng et al. (US 20170104061 A1).
Regarding claim 10, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 9. Peng et al. teaches further comprising:
forming (FIG.30A) an isolation structure (shallow trench isolations (STIs) 412) over the substrate (100); and forming the first bottom layer (first epitaxial layers 102a) adjacent to (FIG.30A) the isolation structure, wherein the first bottom layer has an extending portion ([0030]) in the isolation structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included isolation structure and epitaxial layer arrangement of Peng et al. to structure of Mochizuki et al. as modified by Frougier et al. By forming epitaxial layer extending into STI (isolation structure), Peng et al. provides dielectric isolation between adjacent device regions while allowing s/d epitaxial structure to be formed, thereby reducing parasitic capacitance and improving transistor performance.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1) and Liaw (US 10522546 B2).
Regarding claim 14, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 8. Liaw teaches further comprising:
forming (FIG.3) a dielectric feature (MDL fins 114a) between the first fin structure (semiconductor fin 110) and the second fin structure (semiconductor fin 112); and forming the dummy gate structure (gate structures 118) over the dielectric feature.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the dielectric feature and gate arrangement of Liaw to the structure of Mochizuki et al. as modified by Frougier et al., as the structure taught by Liaw provides electrical isolation between adjacent semiconductor structures while allowing gate structure to extend over intervening region.
Claims 4, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1), Liaw (US 10522546 B2), and Akarvardar et al. (US 8809947 B1).
Regarding claim 4, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 1. Liaw teaches further comprising:
forming (FIG.3) a dielectric feature (MDL fins 114a) between the first fin structure (semiconductor fin 110) and the second fin structure (semiconductor fin 112), wherein the dielectric feature comprises a liner layer (dielectric layer 134a) and a filling layer (dielectric layer 136a) formed over the liner layer.
Liaw does not teach wherein the first dielectric liner layer is in direct contact with the liner layer of the dielectric feature.
However, Akarvardar et al. teaches wherein the first dielectric liner layer (silicon nitride sacrificial liner 30) is in direct contact (FIG.3) with the liner layer (masking layer 16) of the dielectric feature.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure of Mochizuki et al. as modified by Frougier et al. and Liaw to include Liaw’s dielectric feature and Akarvardar et al.’s direct-contact arrangement to define active nanostructures and thereby disable lower nanostructures.
Regarding claim 18, Mochizuki et al. in view of Frougier et al., Liaw, and Akarvardar et al. teaches the method for forming the semiconductor device structure as claimed in claim 16. Mochizuki teaches further comprising:
forming (FIG.6) a first bottom layer (lower epitaxial layer 160) in the first S/D recess (recessed portion 130) and a second bottom layer (lower epitaxial layer 160) in the second S/D recess (recessed portion 130).
Regarding claim 20, Mochizuki et al. in view of Frougier et al., Liaw, and Arkarvar et al. teaches the method for forming the semiconductor device structure as claimed in claim 16. Akarvardar et al. teaches further comprising:
forming (FIG.6) a cladding layer (upper cladding layer 14 + side cladding layer 60) over a top surface and a sidewall surface of the first fin structure (non-planar transistor structure 20, leftside) and a top surface and a sidewall surface of the second fin structure (non-planar transistor structure 20, rightside).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the cladding layers of Akarvardar et al. to the structure of Mochizuki et al. as modified by Frougier et al. and Liaw. By forming cladding material over the top and sidewalls of non-planar semiconductor structure, Akarvardar et al. provides known protective layer over exposed surfaces and thus provides process for tuning transistor performance by region during fabrication.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1), Liaw (US 10522546 B2), Akarvardar et al. (US 8809947 B1), and Huang et al. (US 9793174 B1).
Regarding claim 17, Mochizuki et al. in view of Frougier et al., Liaw, and Arkarvar et al. teaches the method for forming the semiconductor device structure as claimed in claim 16. Huang et al. teaches further comprising:
forming (FIG.9) a first insulating layer (patterned photoresist layer 351) over the first top layer (insulating layer 200).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have include insulating layer arrangement of Huang et al. to the method of Mochizuki et al. as modified by Frougier et al., Liaw, and Akarvardar et al. By forming insulating layers over different portions of device at varying vertical layers, Huang et al. provides a known technique for electrically isolating s/d region from lower layers, such that some stacked nanostructures remain electrically active while others are blocked off for optimization of power versus speed.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1), Liaw (US 10522546 B2), Akarvardar et al. (US 8809947 B1), and Peng et al. (US 20170104061 A1).
Regarding claim 19, Mochizuki et al. in view of Frougier et al., Liaw, and Arkarvar et al. teaches the method for forming the semiconductor device structure as claimed in claim 18. Peng et al. teaches further comprising:
forming (FIG.30A) an isolation structure (shallow trench isolations (STIs) 412) over the substrate (100); and forming the first bottom layer (first epitaxial layers 102a) adjacent to (FIG.30A) the isolation structure, wherein the first bottom layer has an extending portion ([0030]) in the isolation structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included isolation structure and epitaxial layer arrangement of Peng et al. to structure of Mochizuki et al. as modified by Frougier et al., Liaw, and Akarvardar et al. By forming epitaxial layer extending into STI (isolation structure), Peng et al. provides dielectric isolation between adjacent device regions while allowing s/d epitaxial structure to be formed, thereby reducing parasitic capacitance and improving transistor performance.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1), Reznicek (US 20190221640 A1) and Kwon et al. (US 20180301564 A1).
Regarding claim 1, Mochizuki et al. teaches a method for forming a semiconductor device structure ((15)), comprising:
forming a first fin structure (FIG.2, left nanostack) and a second fin structure (FIG.2, right nanostack) over a substrate (102),
wherein the first fin structure comprises a plurality of first semiconductor layers (SiGe layers 105a-105d) and a plurality of second semiconductor layers (Si layers 107a-107c) alternately stacked (FIG.2, left nanostack), and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked (FIG.2, right nanostack);
forming (FIG.2) a dummy gate structure (dummy gate 110) over the first fin structure and the second fin structure;
removing (FIG.2) a portion of the first fin structure and the second fin structure to form a first source/drain (S/D) recess (recessed portion 130) and a second S/D recess (recessed portion 130);
forming (FIG.6) a first bottom layer (lower epitaxial layers 160) in the first S/D recess and a second bottom layer (lower epitaxial layers 160) in the second S/D recess;
Mochizuki et al. does not teach forming a first dielectric liner layer over the first bottom layer; forming a first top layer over the first dielectric liner layer; and forming a first S/D structure over the first top layer and a second S/D structure over the second bottom layer.
However, Frougier et al. teaches forming (FIG.14, 100L) a first top layer (semiconductor mandrel 142) over the first dielectric liner layer (insulative coating 138).
Frougier et al. does not teach forming a first dielectric liner layer over the first bottom layer; and forming a first S/D structure over the first top layer and a second S/D structure over the second bottom layer.
However, Reznicek teaches forming (FIG.9) a first dielectric liner layer (ILD layer 135) over the first bottom layer (arsenic implanted regions 130); and Kwon et al. teaches forming (FIG.2A) a first S/D structure (source/drain regions SD) over the first top layer (top surfaces ts2) and a second S/D structure (source/drain regions SD) over the second bottom layer (growth prevention regions 148).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Frougier et al.’s top layer and dielectric layer arrangement with Reznicek’s dielectric layer and bottom layer arrangement and Kwon et al.’s s/d, top and bottom layers arrangement, and to have provided such arrangement in combination to Mochizuki’s et al.’s recessed s/d regions. Both Mochizuki et al. and Frougier et al. are directed to fabrication of vertically stacked nanostructures with recessed s/d regions; thus, supplying the process steps and structures of Frougier et al., as modified by Reznicek and Kwon et al., to that of Mochizuki et al. predictably enables region-specific effective nanosheet count, ultimately providing power-efficient and high-speed regions on the same chip.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1) and Kwon et al. (US 20180301564 A1).
Regarding claim 11, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 9. Frougier et al. teaches wherein the first top layer (semiconductor mandrel 142) is in direct contact with the first dielectric liner layer (insulative coating 138).
Frougier et al., however, does not teach forming a first top layer over the first bottom layer. Kwon et al. teaches further comprising:
forming (FIG.2A) a first top layer (top surfaces ts2) over the first bottom layer (growth prevention regions 148).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Frougier et al.’s dielectric liner, top semiconductor layer and s/d arrangement to Kwon et al.’s top and bottom layer arrangement, and to have, in combination, supplied such arrangement to Mochizuki’s et al.’s recessed s/d regions. Both Mochizuki et al. and Frougier et al. are directed to fabrication of vertically stacked nanostructures with recessed s/d regions; thus, supplying the process steps and structures of Frougier et al., as modified by Kwon et al., to that of Mochizuki et al. predictably enables region-specific effective nanosheet count, ultimately providing power-efficient and high-speed regions on the same chip.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1) and Reznicek (US 20190221640 A1).
Regarding claim 13, Mochizuki et al. in view of Frougier et al. teaches the method for forming the semiconductor device structure as claimed in claim 8. Frougier et al. further comprising:
forming (FIG.14, region 100S) a second S/D structure (source/drain epitaxial region 150) in the second S/D recess (FIG.5, recess 134),
wherein a bottom surface of first S/D structure is higher than (FIG.14 and claim 9: positioned above) a bottom surface of the second S/D structure.
Frougier et al. does not teach forming a first source/drain (S/D) structure over the first dielectric liner layer.
However, Reznicek teaches forming (FIG.9) a first source/drain (S/D) structure (epitaxial source/drain layers 140) over the first dielectric liner layer (ILD layer 135);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Frougier et al.’s dielectric liner, top semiconductor layer and s/d arrangement to Reznicek’s s/d and dielectric layer arrangement, and to have then, supplied in combination, such arrangement to Mochizuki’s et al.’s recessed s/d regions. Both Mochizuki et al. and Frougier et al. are directed to fabrication of vertically stacked nanostructures with recessed s/d regions; thus, supplying the process steps and structures of Frougier et al., as modified by Reznicek, to that of Mochizuki et al. predictably enables region-specific effective nanosheet count, ultimately providing power-efficient and high-speed regions on the same chip. Frougier et al. supplies layers at different heights in different regions, which enables different effective nanostructure counts for different performance targets in the same fin stack.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 10453824 B1) in view of Frougier et al. (US 9947804 B1), Reznicek (US 20190221640 A1), Liaw (US 10522546 B2), and Akarvardar et al. (US 8809947 B1).
Regarding claim 16, Mochizuki et al. teaches a method for forming a semiconductor device structure, comprising:
forming a first fin structure (FIG.2, left nanostack) and a second fin structure (FIG.2, right nanostack) over a substrate (102),
wherein the first fin structure comprises a plurality of first semiconductor layers (SiGe layers 105a-105d) and a plurality of second semiconductor layers (Si layers 107a-107c) stacked in a vertical direction (z-direction), and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in the vertical direction (FIG.2);
forming (FIG.2) a dummy gate structure (dummy gate 110) over the first fin structure and the second fin structure; and
removing (FIG.2) a portion of the first fin structure and the second fin structure to form a first S/D recess (recessed portion 130) and a second S/D recess (recessed portion 130);
Mochizuki et al. does not teach forming a dielectric feature between the first fin structure and the second fin structure; forming a dummy gate structure over the dielectric feature; forming a first dielectric liner layer adjacent to the first fin structure; forming a first top layer on a sidewall surface of the first dielectric liner layer; forming a first source/drain (S/D) structure over the first dielectric liner layer; and forming a second S/D structure in the second S/D recess, wherein a bottom surface of first S/D structure is higher than a bottom surface of the second S/D structure.
However, Frougier et al. teaches forming (FIG.14, region 100L) a first dielectric liner layer (insulative coating 138) adjacent to the first fin structure (left nanosheet stack 114)
forming (FIG.14, region 100S) a second S/D structure (source/drain epitaxial region 150) in the second S/D recess (FIG.5, recess 134),
wherein a bottom surface of first S/D structure is higher than (FIG.14 and claim 9: positioned above) a bottom surface of the second S/D structure.
Reznicek teaches forming (FIG.9) a first source/drain (S/D) structure (epitaxial source/drain layers 140) over the first dielectric liner layer (ILD layer 135).
Liaw teaches forming (FIG.3) a dielectric feature (MDL fins 114a) between the first fin structure (semiconductor fin 110) and the second fin structure (semiconductor fin 112); and
forming a dummy gate structure (gate structures 118) over the dielectric feature (MDL fins 114a).
Akarvardar et al. teaches forming ((14)) a first top layer (confining material 40, formed by CVD) on a sidewall surface (FIG.4) of the first dielectric liner layer (silicon nitride sacrificial liner 30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mochizuki et al. in view of Frougier et al., Liaw, Reznicek, and Akarvardar et al. to incorporate respective dielectric isolation, s/d region, and semiconductor layer arrangements and thereby establish base for subsequent dielectric isolation, set vertical boundary for conductive region, and ultimately enable use of fewer active nanostructures for power efficiency in one region while another uses more for speed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEANNE M KIM whose telephone number is (571)272-8768. The examiner can normally be reached Monday-Thursday 8:00-6:00.
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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