Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 24, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Claim 8 recites “… extending the trench into the first ILD layer“ (emphasis added). None of the drawings show the trench extending into the first ILD layer. Claim 9, which depends on claim 8 recites “… the trench comprises a first end proximal to an interface between the second and third ILD layers and a second end in the first ILD layer “ (emphasis added). Again, none of the drawings show the second end of the trench in the first ILD layer. Furthermore, claim 13, which depends on claim 12 recites “… the first and second trenches comprise first ends proximal to an interface between the second and third ILD layers and second ends in the first ILD layer “ (emphasis added). Again, none of the drawings show the second end of the trench in the first ILD layer.
Detailed drawings are expected showing every feature of the invention specified in the claims No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8-11 and 13-15 were rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which were not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 8 recites “… extending the trench into the first ILD layer“ (emphasis added). The Examiner could not find any description of this limitation in either the specification or the drawings. Furthermore, claim 13, which depends on claim 12 recites “… the first and second trenches comprise first ends proximal to an interface between the second and third ILD layers and second ends in the first ILD layer “ (emphasis added). Again, the Examiner could not find any description of this limitation in either the specification or the drawings. Appropriate correction/clarification is requested.
Appropriate correction/clarification is requested. Claims 9-11 and 14-15 inherit the 35 U.S.C. 112(a) or 35 U.S.C. 112, 1st paragraph (pre-AIA ) rejections based on their dependencies on claims 8 and 13, respectively.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-11 and 13-15 were rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 8 recites “… extending the trench into the first ILD layer“ (emphasis added). The Examiner could not find any description of this limitation in either the specification or the drawings. Furthermore, claim 13, which depends on claim 12 recites “… the first and second trenches comprise first ends proximal to an interface between the second and third ILD layers and second ends in the first ILD layer “ (emphasis added). Again, the Examiner could not find any description of this limitation in either the specification or the drawings. Appropriate correction/clarification is requested.
Appropriate correction/clarification is requested. Claims 9-11 and 14-15 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112, 2nd paragraph (pre-AIA ) rejections based on their dependencies on claims 8 and 13, respectively.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leobandung (Pub. No.: US 2018/0197946 A1).
Regarding Claim 1, Leobandung discloses a method of manufacturing a semiconductor device, comprising: forming a lower wiring pattern in a first interlayer dielectric (ILD) layer (Par. 0022-0029; Fig. 1 – lower wiring pattern comprising interconnect structure 16/18; first interlayer dielectric (ILD) layer 12); forming a second ILD layer over the lower wiring pattern (Par. 0031-0033; Fig. 2 – second ILD layer 20); forming a trench in the second ILD layer (Par. 0032-0033; Fig. 3 – trench 22); forming a metal-insulator-metal (MIM) structure in the trench and on an upper surface of the second ILD layer, the MIM structure including electrode layers and one or more insulating layers disposed between adjacent electrode layers of the electrode layers (Par. 0033-0044; Figs. 4-12 – metal-insulator-metal (MIM) structure comprising electrode layers 30/30P, 50/50P and 70/70P, insulating layers 40 and 60);
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forming a third ILD layer over the MIM structure (Par. 0045-0047; Fig. 12 – third ILD layer 80); forming an opening in the third ILD layer and the second ILD layer so that the opening passes through one or more of the electrode layers of the MIM structure on the upper surface of the second ILD layer and the lower wiring pattern is exposed at a bottom of the opening (Par. 0046-0051; Fig. 13); and forming a vertical wiring pattern by filling the opening with a conductive material so that the one or more of the electrode layers connect to a side face of the vertical wiring pattern (Par. 0046-0051; Fig. 13 – vertical wiring pattern comprising via structure 86 and conductive line structure 88).
Regarding Claim 2, Leobandung, as applied to claim 1, discloses the method, wherein the vertical wiring pattern includes a via portion and a pad portion disposed on the via portion, and the one or more of the electrode layers is in contact with a side face of the via portion (Par. 0046-0051; Fig. 13 – via portion 86, pad portion 88).
Regarding Claim 3, Leobandung, as applied to claim 1, discloses the method, wherein the forming the MIM structure comprises: (i) forming a blanket layer of a conductive material (Fig. 4 – blanket layer 30 of a conductive material 30); (ii) patterning the blanket layer (Fig. 5 – blanket layer 30 is patterned to form an electrode layer 30P); and (iii) forming a blanket layer of an insulating material (Fig. 6 – blanket layer 40 of an insulating material).
Regarding Claim 4, Leobandung, as applied to claim 3, discloses the method, wherein (i)-(iii) are repeated at least twice (Figs. 4-9).
Regarding Claim 5, Leobandung, as applied to claim 3, discloses the method, wherein a layer of the insulating material is disposed between and in direct contact with the second ILD layer and the third ILD layer (Par. 0040-0046; Fig. 12 – insulating material 60).
Regarding Claim 6, Leobandung, as applied to claim 3, discloses the method, wherein the insulating material includes hafnium oxide (Par. 0036).
Regarding Claim 7, Leobandung, as applied to claim 3, discloses the method, wherein the conductive material includes TiN or Ti. (Par. 0033).
Claims 1-5, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yin et al. (Pub. No.: US 2020/0176557 A1).
Regarding Claim 1, Yin et al. discloses a method of manufacturing a semiconductor device, comprising: forming a lower wiring pattern in a first interlayer dielectric (ILD) layer (Par. 0019 - 0030; Figs. 1-7 – lower wiring pattern 109; first interlayer dielectric (ILD) layer comprising dielectric layer 111 and hard mask layer 117); forming a second ILD layer over the lower wiring pattern (Par. 0019 - 0030; Figs. 1-7 – second ILD layer 119); forming a trench in the second ILD layer (Par. 0019 - 0030; Figs. 1-7 – trench 121); forming a metal-insulator-metal (MIM) structure in the trench and on an upper surface of the second ILD layer, the MIM structure including electrode layers and one or more insulating layers disposed between adjacent electrode layers of the electrode layers (Par. 0032 - 0039; Figs. 1-7 – metal-insulator-metal (MIM) structure comprising electrode layers 203, 303 and 503, insulating layers 301 and 401); forming a third ILD layer over the MIM structure (Par. 0063-0068; Figs. 1-7 – third ILD layer 701);
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forming an opening in the third ILD layer and the second ILD layer so that the opening passes through one or more of the electrode layers of the MIM structure on the upper surface of the second ILD layer and the lower wiring pattern is exposed at a bottom of the opening (Par. 0065-0074; Fig. 7); and forming a vertical wiring pattern by filling the opening with a conductive material so that the one or more of the electrode layers connect to a side face of the vertical wiring pattern (Par. 0065-0074; Fig. 7 – vertical wiring patterns formed of diffusion barrier layer 705 and conductive plugs 707)
Regarding Claim 2, Yin et al., as applied to claim 1, discloses the method, wherein the vertical wiring pattern includes a via portion and a pad portion disposed on the via portion, and the one or more of the electrode layers is in contact with a side face of the via portion (Fig. 7).
Regarding Claim 3, Yin et al., as applied to claim 1, discloses the method, wherein the forming the MIM structure comprises: (i) forming a blanket layer of a conductive material (Par. 0032-0034; Fig. 2); (ii) patterning the blanket layer (Par. 0035-0036; Fig. 2); and (iii) forming a blanket layer of an insulating material (Par. 0037-0038; Fig. 3 – insulating material 301).
Regarding Claim 4, Yin et al., as applied to claim 3, discloses the method, wherein (i)-(iii) are repeated at least twice (Figs. 3-7).
Regarding Claim 5, Yin et al., as applied to claim 3, discloses the method, wherein a layer of the insulating material is disposed between and in direct contact with the second ILD layer and the third ILD layer (Par. 0063-0068; Fig. 3 – the first few monolayers of dielectric layer 701 could be considered to constitute the layer of the insulating material; the rest of the dielectric layer 701 would constitute the third ILD layer).
Regarding Claim 7, Yin et al., as applied to claim 3, discloses the method, wherein the conductive material includes TiN or Ti. (Par. 0033).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 17-20 are rejected under 35 U.S.C. 103 as obvious over Leobandung (Pub. No.: US 2018/0197946 A1) in view of Yin et al. (Pub. No.: US2020/0176557 A1).
Regarding Claim 17, Leobandung discloses
a method of manufacturing a semiconductor device, comprising: forming a first lower wiring pattern and a second lower wiring pattern Par. 0022-0029; Fig. 1 – first lower wiring pattern 16; second lower wiring pattern 18, first interlayer dielectric (ILD) layer 12; a third lower wiring pattern is not shown in any of the Figs. but it’s presence is implied as there are more of such units as shown in Fig. 13); ;
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forming a second ILD layer over the first, second, and third lower wiring patterns (Par. 0031-0033; Fig. 2 – second ILD layer 20); forming a trench in the second ILD layer (Par. 0032-0033; Fig. 3 – multiple trenches 22 are shown); forming a metal-insulator-metal (MIM) structure in the trench and on an upper surface of the second ILD layer, the MIM structure including electrode layers and one or more insulating layers disposed between adjacent electrode layers of the electrode layers (Par. 0033-0044; Figs. 4-12 – metal-insulator-metal (MIM) structure comprising electrode layers 30/30P, 50/50P and 70/70P, insulating layers 40 and 60); forming a third ILD layer over the MIM structure and the second ILD layer (Par. 0045-0047; Fig. 12 – third ILD layer 80); forming a first opening above the first lower wiring pattern and a second opening above the second lower wiring pattern in the third ILD layer and the second ILD layer so that the first and second openings pass through one or more of the electrode layers of the MIM structure on the upper surface of the second ILD layer, wherein the one or more of the electrode layers of the MIM structure through which the second opening passes are different from the one or more of the electrode layers of the MIM structure through which the first openings passes (Par. 0046-0051; Fig. 13); and forming a first vertical wiring pattern and a second vertical wiring pattern by respectively filling the first and second openings with a conductive material so that the one or more of the electrode layers through which the first opening passes connect to a side face of the first vertical wiring pattern, and the one or more of the electrode layers through which the second opening passes connect to a side face of the second vertical wiring pattern (Par. 0046-0051; Fig. 13 – vertical wiring pattern comprising via structure 86 and conductive line structure 88). Leobandung does not explicitly disclose
forming the first lower wiring pattern and a second lower wiring pattern in a memory cell area and the third lower wiring pattern in a logic circuit area. However, Yin et al., at least implicitly, teaches
forming the first lower wiring pattern and a second lower wiring pattern in a memory cell area and the third lower wiring pattern in a logic circuit area (Par. 0002-0003 – this prior art teaches that the metal-insulator-metal capacitors, as employed by Leobandung are in use in both memory cell areas and logic circuit areas; also see Par. 0019 - 0030; Figs. 1-7 – three lower wiring patterns 109 are shown; first interlayer dielectric (ILD) layer comprising dielectric layer 111 and hard mask layer 117). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Yin et al. to adapt a method of manufacturing a semiconductor device, comprising:, forming the first lower wiring pattern and a second lower wiring pattern of Leobandung in a memory cell area and the third lower wiring pattern in a logic circuit area in order to form desired functional circuitries.
Regarding Claim 18, modified Leobandung, as applied to claim 17, discloses the method, further comprising: forming a third opening above the third lower wiring pattern in the third ILD layer and the second ILD layer; and forming a third vertical wiring pattern by filling the third opening with the conductive material (Yin et al. – Par. 0019 – 0030, 0063-0074; Figs. 1-7 – the leftmost opening could be considered as the third opening, third ILD layer 701, second ILD layer 119; vertical wiring patterns formed of diffusion barrier layer 705 and conductive plugs 707).
Regarding Claim 19, modified Leobandung, as applied to claim 18, discloses the method, wherein: an insulating layer made of a same material as the one or more insulating layers of the MIM structure is formed in the logic circuit area, and the third opening passes through the insulating layer (Yin et al. – Par. 0019 – 0030, 0063-0074; Figs. 1-7).
Regarding Claim 20, modified Leobandung, as applied to claim 18, discloses the method, wherein the insulating layer is made of a high-k dielectric material (Yin et al. – Par. 0037).
Claims 17-20 are rejected under 35 U.S.C. 103 as obvious over Yin et al. (Pub. No.: US2020/0176557 A1).
Regarding Claim 17, Yin et al. discloses
a method of manufacturing a semiconductor device, comprising: forming a first lower wiring pattern and a second lower wiring pattern in a memory cell area and a third lower wiring pattern in a logic circuit area, the first, second, and third lower wiring patterns being formed in a first interlayer dielectric (ILD) layer (Par. 0019 - 0030; Figs. 1-7 – first lower wiring pattern 109 - out of the 3 conductive lines 109 shown in Fig. 7, the one in the middle could be considered as the first wiring pattern; the rightmost conductive line 109 could be considered as the second lower wiring pattern; the leftmost conductive line 109 could be considered as the third lower wiring pattern; first interlayer dielectric (ILD) layer comprising dielectric layer 111 and hard mask layer 117); forming a second ILD layer over the first, second, and third lower wiring patterns (Par. 0019 - 0030; Figs. 1-7 – second ILD layer 119); forming a trench in the second ILD layer (Par. 0019 - 0030; Figs. 1-7 – trench 121); forming a metal-insulator-metal (MIM) structure in the trench and on an upper surface of the second ILD layer, the MIM structure including electrode layers and one or more insulating layers disposed between adjacent electrode layers of the electrode layers (Par. 0032 - 0039; Figs. 1-7 – metal-insulator-metal (MIM) structure comprising electrode layers 203, 303 and 503, insulating layers 301, and 401); forming a third ILD layer over the MIM structure and the second ILD layer (Par. 0063-0068; Figs. 1-7 – third ILD layer 701); forming a first opening above the first lower wiring pattern and a second opening above the second lower wiring pattern in the third ILD layer and the second ILD layer so that the first and second openings pass through one or more of the electrode layers of the MIM structure on the upper surface of the second ILD layer, wherein the one or more of the electrode layers of the MIM structure through which the second opening passes are different from the one or more of the electrode layers of the MIM structure through which the first openings passes (Par. 0065-0074; Fig. 7); and forming a first vertical wiring pattern and a second vertical wiring pattern by respectively filling the first and second openings with a conductive material so that the one or more of the electrode layers through which the first opening passes connect to a side face of the first vertical wiring pattern, and the one or more of the electrode layers through which the second opening passes connect to a side face of the second vertical wiring pattern (Par. 0065-0074; Fig. 7 – vertical wiring patterns formed of diffusion barrier layer 705 and conductive plugs 707). Yin et al. does not explicitly disclose
forming the first lower wiring pattern and a second lower wiring pattern in a memory cell area and the third lower wiring pattern in a logic circuit area. However, Yin et al., at least implicitly, teaches
forming the first lower wiring pattern and a second lower wiring pattern in a memory cell area and the third lower wiring pattern in a logic circuit area (Par. 0002-0003 – this prior art teaches that the metal-insulator-metal capacitors, as employed by Yin et al. are in use in both memory cell areas and logic circuit areas; also see Par. 0019 - 0030; Figs. 1-7 – three lower wiring patterns 109 are shown; first interlayer dielectric (ILD) layer comprising dielectric layer 111 and hard mask layer 117). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Yin et al. to adapt a method of manufacturing a semiconductor device, comprising:, forming the first lower wiring pattern and a second lower wiring pattern of Yin et al. in a memory cell area and the third lower wiring pattern in a logic circuit area in order to form desired functional circuitries.
Regarding Claim 18, Yin et al., as applied to claim 17, discloses the method, further comprising: forming a third opening above the third lower wiring pattern in the third ILD layer and the second ILD layer; and forming a third vertical wiring pattern by filling the third opening with the conductive material (Par. 0065-0074; Fig. 7 – vertical wiring patterns formed of diffusion barrier layer 705 and conductive plugs 707).
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Regarding Claim 19, Yin et al., as applied to claim 18, discloses the method, wherein: an insulating layer made of a same material as the one or more insulating layers of the MIM structure is formed in the logic circuit area, and the third opening passes through the insulating layer (Fig. 7).
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Regarding Claim 20, Yin et al., as applied to claim 18, discloses the method, wherein the insulating layer is made of a high-k dielectric material (Par. 0037).
Allowable Subject Matter
Claims 12 and 16 are allowed. The following is an examiner's statement of reasons for allowance:
Regarding Claim 12: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by a method of manufacturing a semiconductor device, comprising: forming a first lower wiring pattern, a second lower wiring pattern, and a third lower wiring pattern in a first interlayer dielectric (ILD) layer; forming a second ILD layer over the first, second, and third lower wiring patterns; forming a first trench and a second trench in the second ILD layer; forming a metal-insulator-metal (MIM) structure in the first and second trenches and on an upper surface of the second ILD layer, the MIM structure including electrode layers and one or more insulating layers disposed between adjacent electrode layers of the electrode layers; forming a third ILD layer over the MIM structure; forming a first opening above the first lower wiring pattern, a second opening above the second lower wiring pattern, and a third opening above the third lower wiring pattern in the third ILD layer and the second ILD layer so that the first, second, and third openings pass through one or more of the electrode layers of the MIM structure on the upper surface of the second ILD layer, wherein the one or more of the electrode layers of the MIM structure through which the third opening passes are different from the one or more of the electrode layers of the MIM structure through which the first and second openings pass; and forming a first vertical wiring pattern, a second vertical wiring pattern, and a third vertical wiring pattern by respectively filling the first, second, and third openings with a conductive material so that the one or more of the electrode layers through which the first opening passes connect to a side face of the first vertical wiring pattern, the one or more of the electrode layers through which the second opening passes connect to a side face of the second vertical wiring pattern, and the one or more of the electrode layers through which the third opening passes connect to a side face of the third vertical wiring pattern.
The most relevant prior art reference due to Leobandung (Pub. No.: US 2018/0197946 A1) substantially discloses a method of manufacturing a semiconductor device, comprising: forming a first lower wiring pattern, a second lower wiring pattern, and a third lower wiring pattern in a first interlayer dielectric (ILD) layer (Par. 0022-0029; Fig. 1 – first lower wiring pattern 16; second lower wiring pattern 18, first interlayer dielectric (ILD) layer 12; a third lower wiring pattern is not shown in any of the Figs. but it’s presence is implied as there are more of such units as shown in Fig. 13); forming a second ILD layer over the first, second, and third lower wiring patterns (Par. 0031-0033; Fig. 2 – second ILD layer 20);; forming a first trench and a second trench in the second ILD layer (Par. 0032-0033; Fig. 3 – multiple trenches 22 are shown); forming a metal-insulator-metal (MIM) structure in the first and second trenches and on an upper surface of the second ILD layer, the MIM structure including electrode layers and one or more insulating layers disposed between adjacent electrode layers of the electrode layers (Par. 0033-0044; Figs. 4-12 – metal-insulator-metal (MIM) structure comprising electrode layers 30/30P, 50/50P and 70/70P, insulating layers 40 and 60); forming a third ILD layer over the MIM structure (Par. 0045-0047; Fig. 12 – third ILD layer 80);
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forming a first opening above the first lower wiring pattern, a second opening above the second lower wiring pattern, and a third opening above the third lower wiring pattern in the third ILD layer and the second ILD layer so that the first, second, and third openings pass through one or more of the electrode layers of the MIM structure on the upper surface of the second ILD layer, Par. 0046-0051; Fig. 13); and forming a first vertical wiring pattern, a second vertical wiring pattern, and a third vertical wiring pattern by respectively filling the first, second, and third openings with a conductive material so that the one or more of the electrode layers through which the first opening passes connect to a side face of the first vertical wiring pattern, the one or more of the electrode layers through which the second opening passes connect to a side face of the second vertical wiring pattern, and the one or more of the electrode layers through which the third opening passes connect to a side face of the third vertical wiring pattern (Par. 0046-0051; Fig. 13).
This prior art, however, does not disclose a method of manufacturing a semiconductor device, comprising: forming a first opening above the first lower wiring pattern, a second opening above the second lower wiring pattern, and a third opening above the third lower wiring pattern in the third ILD layer and the second ILD layer so that the first, second, and third openings pass through one or more of the electrode layers of the MIM structure on the upper surface of the second ILD layer, wherein the one or more of the electrode layers of the MIM structure through which the third opening passes are different from the one or more of the electrode layers of the MIM structure through which the first and second openings pass.
Additionally, Yin et al. (Pub. No.: US2020/0176557 A1) teaches a method of manufacturing a semiconductor device, comprising: forming a first lower wiring pattern, a second lower wiring pattern, and a third lower wiring pattern in a first interlayer dielectric (ILD) layer (Par. 0019 - 0030; Figs. 1-7 – the rightmost conductive line 109 could be considered as the first lower wiring pattern; the leftmost conductive line 109 could be considered as the third lower wiring pattern; the middle conductive line 109 could be considered as the second lower wiring pattern first interlayer dielectric (ILD) layer comprising dielectric layer 111 and hard mask layer 117);
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forming a second ILD layer over the first, second, and third lower wiring patterns (Par. 0019 - 0030; Figs. 1-7 – second ILD layer 119); forming a first trench and a second trench in the second ILD layer (Par. 0019 - 0030; Figs. 1-7 – multiple trenches 121 are shown); forming a metal-insulator-metal (MIM) structure in the first and second trenches and on an upper surface of the second ILD layer, the MIM structure including electrode layers and one or more insulating layers disposed between adjacent electrode layers of the electrode layers (Par. 0032 - 0039; Figs. 1-7 – metal-insulator-metal (MIM) structure comprising electrode layers 203, 303 and 503, insulating layers 301 and 401); forming a third ILD layer over the MIM structure (Par. 0063-0068; Figs. 1-7 – third ILD layer 701); forming a first opening above the first lower wiring pattern, a second opening above the second lower wiring pattern, and a third opening above the third lower wiring pattern in the third ILD layer and the second ILD layer so that the first, second, Par. 0065-0074; Fig. 7); and forming a first vertical wiring pattern, a second vertical wiring pattern, and a third vertical wiring pattern by respectively filling the first, second, and third openings with a conductive material so that the one or more of the electrode layers through which the first opening passes connect to a side face of the first vertical wiring pattern, the one or more of the electrode layers through which the second opening passes connect to a side face of the second vertical wiring pattern, Par. 0065-0074; Fig. 7 – vertical wiring patterns formed of diffusion barrier layer 705 and conductive plugs 707)
This prior art, however, does not disclose a method of manufacturing a semiconductor device, comprising: forming a third opening above the third lower wiring pattern in the third ILD layer and the second ILD layer so that the third openings passes through one or more of the electrode layers of the MIM structure on the upper surface of the second ILD layer, wherein the one or more of the electrode layers of the MIM structure through which the third opening passes are different from the one or more of the electrode layers of the MIM structure through which the first and second openings pass; and forming a third vertical wiring pattern by filling the third opening with a conductive material so that the one or more of the electrode layers through which the third opening passes connect to a side face of the third vertical wiring pattern.
Additionally, the prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. See form PTO-892.
However, none of these prior art references indicated above or the prior arts made of record in form PTO-892, disclose all the limitations of claim 12 (the individual limitations may be found in a plurality of prior arts but there is no motivation to combine). Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, claim 12 is deemed patentable over the prior arts.
Regarding Claim 16: this claim is allowed because of its dependency status from claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fischer (Pub. No.: US 2010/0224960 A1) – This prior art teaches a method of manufacturing a semiconductor device, comprising: forming a lower wiring pattern (341) in a first interlayer dielectric (ILD) layer (340); forming a second ILD layer (410) over the lower wiring pattern; 511 & 521) and one or more insulating layers (611) disposed between adjacent electrode layers of the electrode layers; forming a third ILD layer (420) over the MIM structure; forming an opening in the third ILD layer and the second ILD layer so that the opening passes through one or more of the electrode layers of the MIM structure on the upper surface of the second ILD layer and the lower wiring pattern is exposed at a bottom of the opening (Fig. 2); and forming a vertical wiring pattern (391) by filling the opening with a conductive material so that the one or more of the electrode layers connect to a side face of the vertical wiring pattern (Fig. 2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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10/12/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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