DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 07/24/2024.
Claims 1-20 are pending. Claims 1, 11, and 17 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic CON priority details.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 07/24/2024. This IDS has been considered.
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
9. Claims 1-2, 6-7, 9-12, and 14 is/are rejected under 35 U.S.C. 103 as being obvious over Liaw-290 (US 9,905,290 B2), in view of Liaw-2182 (US 2016/0372182 A1).
Regarding independent claim 1, Liaw-290 teaches a semiconductor device (“SRAM device” employing Fig. 1 circuitry), comprising:
a three-port memory cell (Fig. 1: 100), comprising:
a write port circuit (Fig. 1: 120) comprising a first write pass-gate transistor (Fig. 1: N3) and a second write pass-gate transistor (Fig. 1: N4), and configured to perform a write function according to a write word line (Fig. 1: WWL),
a first write bit line (required global write bit line coupled to Fig. 1: WBL) and a second write bit line (required global write bit line bar coupled to Fig. 1: WBLB);
a first read port circuit (Fig. 1: 130) configured to perform a first read function according to a first read bit line (Fig. 1: RBL1) and a first read word line (Fig. 1: RWL1); and
a second read port circuit (Fig. 1: 140) configured to perform a second read function according to a second read bit line (Fig. 1: RBL2) and a second read word line (Fig. 1: RWL2),
wherein a first gate structure of the first write pass-gate transistor (Fig. 1: gate of N3) and a second gate structure of the second write pass-gate transistor (Fig. 1: gate of N4) are connected to a write word line landing pad (See col. 7, lines 20-29: “landing pad” which is Fig. 1: NWWL1, NWWL2), and the write word line landing pad is connected to the write word line (Fig. 1: WWL. See col. 7, lines 20-29),
wherein the first read bit line (Fig. 3A, Fig. 4A: 316 which is Fig. 1: RBL1), the second read bit line (Fig. 3A, Fig. 4A: 318 which is Fig. 1: RBL2), and the write word line landing pad (Fig. 3A, Fig. 4A: 322, 324 which is Fig. 1: NWWL1, NWWL2) extend in the first direction in a first metallization layer (col. 8, lines 30-32: “…302-328 extend along direction Y in a first metal layer…”),
wherein the write word line (Fig. 4A: 402 which is Fig. 1: WWL) extends in a second direction in a second metallization layer (col. 8, lines 34-36: “… 402…extend along direction X in a second metal layer…”)
wherein the first write bit line and the second write bit line extend in the first direction in a third metallization layer,
wherein the first read word line (Fig. 4A: 422 which is Fig. 1: RWL1) and the second read word line (Fig. 4A: 424 which is Fig. 1: RWL2) extend in the second direction in a fourth metallization layer (col. 8, lines 38-39: “…422 and 424 extend along direction X in a fourth metal layer over the third metal…”),
wherein the first direction is perpendicular to the second direction (see Fig. 3A, Fig. 4A: X, Y directions), and
the third and fourth metallization layers are different from the first and second metallization layers (see Fig. 6 metallization structure in context of col. 8, lines 30-49),
wherein the first metallization layer is the lowest metallization layer, the second metallization layer is formed between the first and third metallization layers (see Fig. 6 metallization structure in context of col. 8, lines 30-49), and the third metallization layer is formed between the second and fourth metallization layers (see Fig. 6 metallization structure in context of col. 8, lines 30-49).
Liaw-290 teaches WBL, WBLB portions in metal layer extending in Y direction; However, Liaw-290 is silent with respect to “the first write bit line and the second write bit line extend in the first direction in a third metallization layer”.
Liaw-2182 teaches the first write bit line and the second write bit line extend in the first direction in a third metallization layer (para [0046]: "...Metal lines for a global write bit line ...an inverse global write bit line ...are contained within the M3 layer..." and they run in Y-direction. See also para [0059], Fig. 8A).
Both Liaw-290 and Liaw-2182 are in the same field of endeavor of read/ write operation of multi-port SRAM device and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Liaw-2182’s M-3 write bit line structure into the apparatus of Liaw-290 such that claimed limitation “the first write bit line and the second write bit line extend in the first direction in a third metallization layer” can be implemented in order to increase operational speed since overall resistance of metal is reduced (Liaw-2182 para [0046]). Other benefits include reducing lateral chip space/ improving layout and improve connection between two chip regions (Liaw-2182 para [0002]).
Regarding claim 2, Liaw-290 and Liaw-2182 teach the semiconductor device as claimed in claim 1. Liaw-290 teaches wherein a first source/drain contact of the first write pass-gate transistor (Fig. 1: ND of N3 transistor) is connected to the second write bit line (Fig. 1: WBLB) through a first write bit line landing pad (Fig. 1: NDB contact region) and a second write bit line landing pad (Fig. 1: NWBLB contact region), and wherein a second source/drain contact of the second write pass-gate transistor (Fig. 1: NDB of N4 transistor) is connected to the first write bit line (Fig. 1: WBL) through a third write bit line landing pad (Fig. 1: ND contact region) and a fourth write bit line landing pad (Fig. 1: NWBL contact region).
Regarding claim 6, Liaw-290 and Liaw-2182 teach the semiconductor device as claimed in claim 1. Liaw-290 teaches wherein the first read port circuit (Fig. 1: 130) further comprises a first read pass-gate transistor (Fig. 1: N6) and a first read pull-down transistor (Fig. 1: N5) connected in series (Fig. 1), and wherein the second read port circuit further comprises a second read pass-gate transistor (Fig. 1: N8) and a second read pull-down transistor (Fig. 1: N7) connected in series (Fig. 1).
Regarding claim 7, Liaw-290 and Liaw-2182 teach the semiconductor device as claimed in claim 6. Liaw-290 teaches wherein the three-port memory cell further comprises:
a first gate structure (Fig. 2: 242), a second gate structure (Fig. 2: 232), a third gate structure (Fig. 2: 234) and a fourth gate structure (Fig. 2: 246) extending in the second direction (Fig. 2: X), wherein the first, second, third and fourth gate structures form channel regions of the first read pass-gate transistor, the first read pull-down transistor, the second read pull-down transistor, and the second read pass-gate transistor (col. 5, lines 49-67, col. 6, lines 1-15: overlap with 214a-b and 218a-b), respectively, wherein the second and third gate structures are disposed between the first and fourth gate structures (Fig. 2 in context of col. 5, lines 49-67, col. 6, lines 1-15).
Regarding claim 9, Liaw-290 and Liaw-2182 teach the semiconductor device as claimed in claim 6. Liaw-290 teaches wherein the write port circuit (Fig. 1: 120 and associated components) further comprises: a first write pull-up transistor (Fig. 1: P1) and a first write pull-down transistor (Fig. 1: N1) connected in series; and a second write pull-up transistor (Fig. 1: P2) and a second write pull-down transistor (Fig. 1: N2) connected in series (these transistors in the memory cell are being used during write process).
Regarding claim 10, Liaw-290 and Liaw-2182 teach the semiconductor device as claimed in claim 1. Liaw-290 teaches wherein the first write pull-up transistor (Fig. 2: 222), the first write pull-down transistor (Fig. 2: 212a-b) and the first read pull-down transistor (Fig. 2: 214a-b) share a first gate structure (Fig. 2: 232) extending in the second direction (Fig. 2: X direction), and
the second write pull-up transistor (Fig. 2: 224), the second write pull-down transistor (Fig. 2: 216a-b) and the second read pull-down transistor (Fig. 2: 218a-b) share a second gate structure (Fig. 2: 234) extending in the second direction (Fig. 2: X direction).
Regarding independent claim 11, Liaw-290 teaches a semiconductor device (“SRAM device” employing Fig. 1 circuitry), comprising:
a three-port memory cell (Fig. 1: 100), comprising:
a write port circuit (Fig. 1: 120 and associated cell components) configured to perform a write function according to a write word line (Fig. 1: WWL), a first write bit line (required global write bit line coupled to Fig. 1: WBL) and a second write bit line (required global write bit line coupled to Fig. 1: WBLB), and comprising:
a first write pull-up transistor (Fig. 1: P1) coupled between a supply voltage (Fig. 1: NVDD1, NVDD2) and the first write bit line (required global write bit line coupled to Fig. 1: WBL); and
a second write pull-up transistor (Fig. 1: P2) coupled between the supply voltage (Fig. 1: NVDD1, NVDD2) and the second write bit line (required global write bit line coupled to Fig. 1: WBLB);
a first read port circuit (Fig. 1: 130) comprising a first read word line (Fig. 1: RWL1) and a first read pass-gate transistor (Fig. 1: N6) and a first read pull-down transistor (Fig. 1: N5) connected in series between a ground (Fig. 1: NVSS3) and a first read bit line (Fig. 1: RBL1);
a second read port circuit (Fig. 1: 140) comprising a second read word line (Fig. 1: RWL2) and a second read pass-gate transistor (Fig. 1: N7) and a second read pull-down transistor (Fig. 1: N8) connected in series between the ground (Fig. 1: NVSS4) and a second read bit line (Fig. 1: RBL2); and
a first gate structure (Fig. 2: 242 “gate structure”), a second gate structure (Fig. 2: 232 “gate structure”), a third gate structure (Fig. 2: 234 “gate structure”), and a fourth gate structure (Fig. 2: 246 “gate structure”) extending in a first direction (Fig. 2: X direction),
wherein the first read bit line (Fig. 3A, Fig. 4A: 316 which is Fig. 1: RBL1) and the second read bit line (Fig. 3A, Fig. 4A: 318 which is Fig. 1: RBL2) extend in a second direction in a first metallization layer (col. 8, lines 30-32: “…302-328 extend along direction Y in a first metal layer…”), and
the write word line (Fig. 4A: 402 which is Fig. 1: WWL) extends in the first direction in a second metallization layer over the first metallization layer (col. 8, lines 34-36: “… 402…extend along direction X in a second metal layer…”),
wherein the first write bit line and the second write bit line extend in the second direction in a third metallization layer over the second metallization layer, and
the first read word line (Fig. 4A: 422 which is Fig. 1: RWL1) and the second read word line (Fig. 3A, Fig. 4A: 424 which is Fig. 1: RWL2) extend in the first direction in a fourth metallization layer over the third metallization layer (col. 8, lines 38-39: “…422 and 424 extend along direction X in a fourth metal layer over the third metal…”),
wherein the first, second, third and fourth gate structures form channel regions (Fig. 2: gate structures 242, 232, 234, 246 combined with active structures 214a-b and 218a-b forms channel) of the first read pass-gate transistor (Fig. 1: N6), the first read pull-down transistor (Fig. 1: N5. See Fig. 2), the second read pull-down transistor (Fig. 1: N7), and the second read pass-gate transistor (Fig. 1: N8. See col. 5, lines 49-67, col. 6, lines 1-15; Fig. 2), respectively,
wherein the first write pull-up transistor (Fig. 1: P1. See Fig. 2: 222 with gate 232) and the first read pull-down transistor (Fig. 1: N5. See Fig. 2: 214a-b with gate 232) share the second gate structure (Fig. 2: 232), and
the second write pull-up transistor (Fig. 1: P2. See Fig. 2: 224 with gate 234) and the second read pull-down transistor (Fig. 1: N7. See Fig. 2) share the third gate structure (Fig. 2: 234).
Liaw-290 teaches WBL, WBLB portions in metal layer extending in Y direction; However, Liaw-290 is silent with respect to the first write bit line and the second write bit line extend in the first direction in a third metallization layer.
Liaw-2182 teaches the first write bit line and the second write bit line extend in the first direction in a third metallization layer (para [0046]: "...Metal lines for a global write bit line ...an inverse global write bit line ...are contained within the M3 layer..." and they run in Y-direction. See also para [0059], Fig. 8A).
Both Liaw-290 and Liaw-2182 are in the same field of endeavor of read/ write operation of multi-port SRAM device and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Liaw-2182’s M-3 write bit line structure into the apparatus of Liaw-290 such that claimed limitation “the first write bit line and the second write bit line extend in the first direction in a third metallization layer” can be implemented in order to increase operational speed since overall resistance of metal is reduced (Liaw-2182 para [0046]). Other benefits include reducing lateral chip space/ improving layout and improve connection between two chip regions (Liaw-2182 para [0002]).
Regarding claim 12, Liaw-290 and Liaw-2182 teach the semiconductor device as claimed in claim 11. Liaw-290 teaches wherein the first metallization layer is the lowest metallization layer, the second metallization layer is formed between the first and third metallization layers, and the third metallization layer is formed between the second and fourth metallization layers (See Fig. 6 disclosure).
Regarding claim 14, Liaw-290 and Liaw-2182 teach the semiconductor device as claimed in claim 11. Liaw-290 teaches wherein the write port circuit further comprises a first write pass-gate transistor (Fig. 1: N3), a second write pass-gate transistor (Fig.1: N4), a first write pull-down transistor (Fig. 1: P1), and a second write pull-down transistor (Fig. 1: N1).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
US 20240040763 A1: disclosure applicable for double patenting rejection.
US 2011/0068413 A1: Fig. 1-Fig. 16 disclosure applicable for all claims.
FUJIWARA et al. (US 2015/0357279 A1): Fig. 7A-7B applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Allowable Subject Matter
Claims 17-20 are indicated as allowable.
Claims 3-5, 8, 13, 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims as described in details ion the following:
Claim 3. “… first write bit line landing pad and the third write bit line landing pad extend in the first direction in the first metallization layer, and wherein the second write bit line landing pad and the fourth write bit line landing pad extend in the second direction in the second metallization layer.”
Claim 4. “… a first VSS conductor extending in the first direction in the first metallization layer, wherein the first VSS conductor is adjacent the second read bit line, wherein the second read bit line is disposed between the first VSS conductor and the first read bit line or the first VSS conductor is disposed between the first and second read bit lines.”
Claim 5. “… a second VSS conductor extending in the first direction in the third metallization layer, wherein the second VSS conductor is disposed between the first and second write bit lines, and the first and second write bit lines are wider than the second VSS conductor.”
Claim 8. “… the first, second, third and fourth gate structures have a gate pitch, and a cell height of the three-port memory cell in the first direction is the same as 4 times the gate pitch.”
Claim 13. “… the first, second, third and fourth gate structures have a gate pitch, and a cell height of the three-port memory cell in the first direction is the same as 4 times the gate pitch.”
Claim 15. “… the first and second read pass-gate transistors and the first and second read pull-down transistors share a first active structure extending in the second direction, wherein the first and second write pass-gate transistors and the first and second write pull-down transistors share a second active structure extending in the second direction, wherein the first and second write pull-up transistors share a third active structure extending in the second direction, and wherein the second active structure is disposed between the first and third active structures.”
Claim 16. “…a fifth gate structure and a sixth gate structure extending in the first direction, wherein the fifth gate structure is aligned with the first gate structure in the first direction, and the sixth gate structure is aligned with the fourth gate structure in the first direction, wherein the first write pull-up transistor, the first write pull-down transistor and the first read pull-down transistor share the second gate structure, and the second write pull-up transistor, the second write pull-down transistor and the second read pull-down transistor share the third gate structure.”
Claims 17-20: “…forming a first VSS conductor that extends in the first direction in the first metallization layer, wherein the first VSS conductor is adjacent the second read bit, wherein the second read bit line is disposed between the first VSS conductor and the first read bit line or the first VSS conductor is disposed between the first and second read bit lines,
forming a second VSS conductor and a third VSS conductor that extend in the second direction in the second metallization layer, wherein the second and third VSS conductors are electrically connected to the first VSS conductor; and
forming a fourth VSS conductor and a fifth VSS conductor that extend in the first direction in the third metallization layer, wherein the fourth and fifth VSS conductors are electrically connected to the second and third VSS conductors.”
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825