CTNF 18/782,900 CTNF 91257 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-3, 6, 10 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chou et al. (US 20100055897 A1; hereinafter “Chou”) . In re claim 1, Chou discloses in figs. 1-2, a method comprising: forming a first conductive feature 5 extending through a first dielectric layer 10 (fig. 1A; ¶12); depositing a second dielectric layer 14 over the first conductive feature 5 and the first dielectric layer 10 (fig. 1A; ¶13); patterning an opening 82 in the second dielectric layer 14 to expose the first conductive feature 5 (fig. 1E; ¶18); etching the first conductive feature 5 to extend the opening below a bottommost surface of the second dielectric layer 14 (fig. 1F; ¶19), wherein etching the first conductive feature 5 comprises immersing the first conductive feature 5 in a solution comprising deionized (DI) water (fig. 1F; ¶19, 22); and forming a second conductive feature in the opening and electrically connected to the first conductive feature (fig. 1F; ¶22; “the via opening 82 is subsequently filled with copper metal”. Hereinafter “ COND2 ”). In re claim 2, Chou discloses in figs. 1-2, the method of claim 1, wherein patterning the opening further comprises etching through an etch stop layer 12 between the first conductive feature 5 and the second conductive feature ( COND2 ). In re claim 3, Chou discloses in figs. 1-2, the method of claim 1, wherein an interface 5a between the first conductive feature 5 and the second conductive feature ( COND2 ) is concave (fig. 1F; ¶22). In re claim 6, Chou discloses in figs. 1-2, the method of claim 1, wherein second conductive feature ( COND2 ) has a same material composition that extends continuously from a first sidewall of the second dielectric layer 14 to a second sidewall of the second dielectric layer 14 (fig. 1F; ¶22; “the via opening 82 is subsequently filled with copper metal”). In re claim 10, Chou discloses in figs. 1-2, the method of claim 1, further comprising forming an etch stop layer 12 between the first dielectric layer 10 and the second dielectric layer 14 (fig. 1A; ¶12), wherein the etch stop layer 12 contacts a lateral surface of the second conductive feature ( COND2 ) (fig. 1F; ¶22; “the via opening 82 is subsequently filled with copper metal”. Therefore, the lateral surface of the filled copper metal is contacted by the etch stop layer 12) . 07-15-aia AIA Claim(s) 17, 18 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Edelstein et al. (US 20170345739 A1; hereinafter “Edelstein”) . In re claim 17, Edelstein discloses in figs. 2-13, a method comprising: forming a diffusion barrier layer 207 (¶32) in a first dielectric layer 201 (“Insulators can also be used as substrates”; ¶22, 29); forming a first contact 209 in the first dielectric layer 201 , the first contact having a concave top surface (fig. 11; ¶38), wherein the concave top surface of the first contact (i.e., the concave top surface of the contact 209 in the aperture 214) extends continuously from a first sidewall of the diffusion barrier layer (e.g., left sidewall of 207) to a second sidewall of the diffusion barrier layer (e.g., right sidewall of 207) ; forming an etch stop layer 211 over the first dielectric layer 201 (¶36); and forming a second contact 215, 217 extending through the etch stop layer 211 to touch the concave top surface of the first contact 209 (figs. 12-13; ¶39-40). In re claim 18, Edelstein discloses in figs. 2-13, the method of claim 17, wherein the second contact 215, 217 has a different material composition than the first contact 209 (the second contact layer 215 includes Ta, Ti, W, Co, Ru, and their nitride materials, TaN, TiN, WN, CoN, RuN; and first contact 209 includes copper seed layer. ¶33, 39) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim (s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou , as applied to claim 1 above, and further in view of Wang et al. (US 20160190007 A1; hereinafter “Wang”) . In re claim 4, Chou discloses in figs. 1-2, the method of claim 1 outlined above. Chou does not expressly disclose wherein forming the second conductive feature comprises a bottom-up deposition process. In the same field of endeavor, Wang discloses in figs. 1-2, a method comprising forming a second conductive feature comprises a bottom-up deposition process. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the second conductive feature of Chou by a bottom-up deposition process as Wang teaches realizing bottom-up filling reduces the possibility of seams or voids, improves the hole filing speed, makes the surface copper thin, reduces the post manufacturing cost and provides technical guarantee for the 3D-TSV encapsulation mass production (¶10 of Wang). In re claim 5, Chou , as modified by Wang , discloses the method of claim 4 outlined above. Wang further wherein forming the second conductive feature comprises forming the second conductive feature without plasma (Based on the method steps described in ¶33-50, the second conductive feature is formed without plasma) . 07-22-aia AIA Claim (s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen , as applied to claim 1 above, and further in view of Cheng et al. (US 20190006515 A1; hereinafter “Cheng”) . In re claim 7, Chen discloses in figs. 1-2, wherein the second conductive feature 206 comprises tungsten (¶55). Chen discloses the first conductive feature (i.e., the metal gate electrode) comprises a metal, e.g., aluminum, but does not expressly disclose the first conductive feature comprises cobalt. In the same field of endeavor, Cheng discloses in figs. 11-20, a method, wherein a first conductive feature 150 (i.e., a metal gate electrode) comprises aluminum or cobalt (¶59). Based on Cheng ’s teachings, a metal gate electrode can be alternately connected by either aluminum or cobalt. One of ordinary skill in the art could have substituted Cheng ’s cobalt-based metal gate electrode on Chen ’s aluminum-based metal gate electrode and predictable results of the work function tuning, lower gate resistance and reduced leakage current can be obtained. MPEP § 2143(I)(B) states “Simple Substitution of One Known Element for Another To Obtain Predictable Results” is prima facie case of obviousness. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng and Chen to arrive at the claimed invention . 07-21-aia AIA Claim (s) 1, 8, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Adusumilli et al. (US 20180053721 A1; hereinafter “Adusumilli”) in view of Chiang et al. (US 20140231932 A1; hereinafter “Chiang”) . In re claim 1, Adusumilli discloses in figs. 1-7, a method comprising: forming a first conductive feature 32B extending through a first dielectric layer 18, 16 (figs. 3-4; ¶44-45); depositing a second dielectric layer 36 over the first conductive feature 32B and the first dielectric layer 18, 16 (fig. 5; ¶47); patterning an opening 38B in the second dielectric layer 36 to expose the first conductive feature 32B (fig. 5; ¶47); etching the first conductive feature 32B to extend the opening 40B below a bottommost surface of the second dielectric layer 36 (fig. 5; ¶47), wherein etching the first conductive feature 32B comprises wet etching (¶43, 50; “Examples of gouging processes that may be used in providing the gouging feature 29 include argon plasma sputtering, reactive ion etching, or a wet etch” and “Each gouging feature 40A, 40B can be formed utilizing one of the gouging processes mentioned above for forming gouging feature 29”); and forming a second conductive feature 42B, 44B in the opening 38B and electrically connected to the first conductive feature 32B (figs. 5-7; ¶47, 52-54). Adusumilli discloses wherein etching the first conductive feature 32B comprises wet etching, but does not expressly disclose immersing the first conductive feature in a solution comprising deionized (DI) water. In the same field of endeavor, Chiang discloses in figs. 1, 3, a method of forming contacts on metal gate comprising: a wet etching process, wherein immersing a first conductive feature 109 (¶23-24) in a solution comprising deionized (DI) water (¶38-40). Based on Chiang ’s teachings of the list of solutions for wet etching of the conductive feature described above, one of ordinary skill in the art would have experimented and used a solution comprising deionized (DI) water, as choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success (e.g., forming contacts to reduce the resistance of a metal gate for the transistors) would be considered as an obvious to try rationale (see MPEP §2143-I E). A person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If the leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. Pfizer, Inc. v. Apotex, Inc ., 480 F.3d 1348, 82 USPQ2d 1321 (Fed. Cir. 2007). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chiang with Adusumilli to arrive at the claimed invention. In re claim 8, Adusumilli , as modified by Chiang , discloses the method of claim 1. Adusumilli further discloses in figs. 1-7, the method further comprising: forming a third conductive feature 20, 22, 24, 30A, 32A extending through the first dielectric layer 18, 26 (¶38, 46); and forming a fourth conductive feature 42A, 44A extending through the second dielectric layer 36 and having a lower convex surface 40A extending into the third conductive feature 20, 22, 24, 30A, 32A (¶47). In re claim 9, Adusumilli , as modified by Chiang , discloses the method of claim 8. Adusumilli further discloses in figs. 1-7, wherein the third conductive feature 20, 22, 24, 30A, 32A extends to a top surface of a source/drain region 14, 12 (¶25) . 07-21-aia AIA Claim (s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Adusumilli et al. (US 20180053721 A1; hereinafter “Adusumilli”) in view of Kim et al. (US 20180083002 A1; hereinafter “Kim”) and Yang et al. (US 20080254624 A1; hereinafter “Yang”) . In re claim 11, Adusumilli discloses in figs. 1-7, a method comprising: forming a gate structure (gate region is formed underneath gate contact opening 28B; hereinafter “GS”) on a substrate 10 (fig. 1; ¶19-20); forming a first dielectric layer 16 surrounding the gate structure GS (fig. 1; ¶19); forming a second dielectric layer 18, 26 over the first dielectric layer 16 (fig. 1; ¶19-20); forming a first conductive feature 32B extending through the second dielectric layer 18, 26 to the gate structure GS (fig. 4; ¶45), forming a conductive liner 30B along sidewalls and a bottom surface of the first conductive feature 32B (fig. 4; ¶46); forming a third dielectric layer 36 over the first dielectric layer 16 (fig. 5; ¶47); and forming a second conductive feature 42B, 44B extending through the third dielectric layer 36 and having a lower convex surface 40B extending into the first conductive feature 32B (figs. 5-7; ¶47, 52-54). Adusumilli discloses wherein the second dielectric layer 18, 26 extends to a level of a top surface of the first conductive feature 32B , but does not expressly disclose: wherein the second dielectric layer extends from a level of the gate structure. In the same field of endeavor, Kim discloses in figs. 4A-4W, a method of forming a gate contact on a high-k metal gate electrode, wherein a second dielectric layer 180, 164 extends from a level of a gate structure (118, GL) to a level of a top surface of a first conductive feature CP2 which is a contact plug on the gate structure (118, GL) (fig. 4W; ¶35-39, 44). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kim into the structure of Adusumilli. One would have been motivated to do so as Kim teaches this would help maintain isolation margins while reducing the interval between an interconnection layer and a contact in down-scaled devices (¶3-6 of Kim ). Adusumilli , as modified by Kim , does not expressly disclose wherein the lower convex surface of the second conductive feature extends from a first sidewall of the conductive liner to a second sidewall of the conductive liner. In the same field of endeavor, Yang discloses in figs. 4-10, a method of forming an improved metal cap for interconnect structures, wherein a lower convex surface of a second conductive feature ( 121, 122a 122b ) (¶36) extends from a first sidewall of a conductive liner 114 to a second sidewall of the conductive liner 114 (¶31) of a first conductive feature 112 (¶15, 35-36; “the at least one etched undercut feature extends along an entire surface of the interconnect element”. Based on teachings in ¶15, 35-26, the undercut areas 118a, 118b extends along an entire surface of the interconnect element 112 and the lower convex surface of a second conductive feature ( 121, 122a 122b ) is an upper surface of the undercut areas 118a, 118b. Therefore, a lower convex surface of a second conductive feature ( 121, 122a 122b ) extends from a first sidewall of a conductive liner 114 to a second sidewall of the conductive liner 114 of a first conductive feature 112 ). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Yang into the structure of Adusumilli/Kim in order to form interconnect structures with improved metal caps which would provide better electromigration resistance (¶2, 8 of Yang ). In re claim 12, Adusumilli , as modified by Kim and Yang , discloses the method of claim 11. Adusumilli further discloses in figs. 1-7, wherein the first conductive feature 32B is made of a different material than the second conductive feature 42B, 44B (“Each second metallization structure 44A, 44B may include a same or different low resistivity metal or metal alloy as that which provides each first metallization structure 32A, 32B”; ¶ 0053). In re claim 13, Adusumilli , as modified by Kim and Yang , discloses the method of claim 11. Adusumilli further discloses in figs. 1-7, the method further comprising forming an etch stop layer 34 (¶ 0047-0048) between the second dielectric layer 18, 26 and the third dielectric layer 36 , wherein the etch stop layer 34 contacts a lateral surface of the second conductive feature 42B, 44B . In re claim 14, Adusumilli , as modified by Kim and Yang , discloses the method of claim 13, wherein the lower convex surface (i.e., a lower convex surface of a second conductive feature ( 121, 122a 122b ) in figs. 4-10 of Yang ) contacts a bottom surface of the etch stop layer (Yang: 106) . In re claim 15, Adusumilli , as modified by Kim and Yang , discloses the method of claim 13, Adusumilli further discloses in figs. 1-7, wherein the etch stop layer 34 contacts a top surface of the conductive liner 30B . 07-22-aia AIA Claim (s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Adusumilli, as modified by Kim and Yang , as applied to claim 11 above, and further in view of Wang et al. (US 20160190007 A1; hereinafter “Wang”) . In re claim 16, Adusumilli , as modified by Kim and Yang , the method of claim 11 outlined above. Adusumilli , as modified by Kim and Yang , does not expressly disclose wherein forming the second conductive feature comprises a bottom-up deposition process. In the same field of endeavor, Wang discloses in figs. 1-2, a method comprising forming a second conductive feature comprises a bottom-up deposition process. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the second conductive feature of Adusumilli , as modified by Kim and Yang, by a bottom-up deposition process as Wang teaches realizing bottom-up filling reduces the possibility of seams or voids, improves the hole filing speed, makes the surface copper thin, reduces the post manufacturing cost and provides technical guarantee for the 3D-TSV encapsulation mass production (¶10 of Wang) . 07-21-aia AIA Claim (s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Adusumilli et al. (US 20180053721 A1; hereinafter “Adusumilli”) in view of Yang et al. (US 20080254624 A1; hereinafter “Yang”) . In re claim 17, Adusumilli discloses in figs. 1-7, a method comprising: forming a diffusion barrier layer 30B in a first dielectric layer 18, 26 (figs. 3-4; ¶44-45); forming a first contact 32B in the first dielectric layer 18, 26 , the first contact having a concave top surface 40B (fig. 5; ¶47), forming an etch stop layer 34 over the first dielectric layer 18, 26 (fig. 5; ¶47-48); and forming a second contact 42B, 44B extending through the etch stop layer 34 to touch the concave top surface of the first contact 40B (figs. 6-7; ¶54). wherein the concave top surface of the first contact 40B extends continuously from a first sidewall of the diffusion barrier layer to a second sidewall of the diffusion barrier layer. In the same field of endeavor, Yang discloses in figs. 4-10, a method of forming an improved metal cap for interconnect structures, wherein a concave top surface of a first contact 112 extends continuously from a first sidewall of the diffusion barrier layer 114 to a second sidewall of the diffusion barrier layer 114 (¶15, 35-36; “the at least one etched undercut feature extends along an entire surface of the interconnect element”. Based on teachings in ¶15, 35-26, the undercut areas 118a, 118b extends along an entire surface of the interconnect element 112. Hence, a concave top surface of a first contact 112 extends continuously from a first sidewall of the diffusion barrier layer 114 to a second sidewall of the diffusion barrier layer 114 ). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Yang into the structure of Adusumilli/Kim in order to form interconnect structures with improved metal caps which would provide better electromigration resistance (¶2, 8 of Yang ) . 07-22-aia AIA Claim (s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Edelstein , as applied to claim 18 above and further in view of Park et al. (US 20190279910 A1; hereinafter “Park”) . In re claim 19, Edelstein discloses a method of claim 18 outlined above. Edelstein does not expressly disclose wherein the first contact comprises cobalt, and wherein the second contact comprises tungsten. In the same field of endeavor, Park discloses in figs. 1-5, a method, wherein a lower contact 22 comprises cobalt, and wherein an upper contact 26 formed on the lower contact comprises tungsten (¶25). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the first contacts and second contacts of Edelstein comprising cobalt, and tungsten, respectively to improve contact formation process in the middle-of-line and back-end-of-line and enhance device yield . 07-22-aia AIA Claim (s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Adusumilli, as modified by Yang , as applied to claim 17 above, and further in view of Cheng et al. (US 20190006515 A1; hereinafter “Cheng”) . In re claim 20, Adusumilli , as modified by Yang , discloses the method of claim 17. Adusumilli further discloses in figs. 1-7, wherein the first contact 32B and the second contact 42B, 44B are electrically connected to a gate of a transistor (gate region is formed underneath gate contact opening 28B; ¶19-20). Adusumilli discloses the gate of the transistor is a functional gate structure that includes a gate stack of a gate dielectric material and a gate conductor. Adusumilli does not expressly disclose the gate conductor is a metal gate. In the same field of endeavor, Cheng discloses in figs. 11-20, a method of forming a gate contact on a high-k metal gate electrode, wherein the gate conductor 150 is a metal gate (¶59). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Cheng into Adusumilli’s gate conductor to arrive at the claimed invention. One of ordinary skill in the art could have substituted Cheng ’s metal-based gate electrode on Adusumilli ’s gate conductor and predictable results of the work function tuning, lower gate resistance and reduced leakage current can be obtained. MPEP § 2143(I)(B) states “Simple Substitution of One Known Element for Another To Obtain Predictable Results” is prima facie case of obviousness. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NILUFA RAHIM/Primary Examiner, Art Unit 2893 Application/Control Number: 18/782,900 Page 2 Art Unit: 2893 Application/Control Number: 18/782,900 Page 3 Art Unit: 2893 Application/Control Number: 18/782,900 Page 4 Art Unit: 2893 Application/Control Number: 18/782,900 Page 5 Art Unit: 2893 Application/Control Number: 18/782,900 Page 6 Art Unit: 2893 Application/Control Number: 18/782,900 Page 7 Art Unit: 2893 Application/Control Number: 18/782,900 Page 8 Art Unit: 2893 Application/Control Number: 18/782,900 Page 9 Art Unit: 2893 Application/Control Number: 18/782,900 Page 10 Art Unit: 2893 Application/Control Number: 18/782,900 Page 11 Art Unit: 2893 Application/Control Number: 18/782,900 Page 12 Art Unit: 2893 Application/Control Number: 18/782,900 Page 13 Art Unit: 2893 Application/Control Number: 18/782,900 Page 14 Art Unit: 2893 Application/Control Number: 18/782,900 Page 15 Art Unit: 2893
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