Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Objections
Claim 6 is objected to because of the following informalities:
Claim 6 recites “the first number of nanostructures stacked one over another over a first anti-punch-through (APT) feature” and “second number of nanostructures stacked one over another over a second APT feature.” The recitations are grammatically incomplete. It appears that “are” has been inadvertently omitted after “nanostructures” in each recitation.
Appropriate correction is required.
Claim 16 is objected to because of the following informalities:
In claim 16, “the first umber” should be corrected to read “the first number.”
Appropriate correction is required.
In claim 17, “the first number of nanostructures stacked one over another over a first APT feature” is grammatically incomplete. It appears that “are” has been inadvertently omitted after “nanostructures.” Similarly, “second number of nanostructures stacked one over another over a second APT feature” is grammatically incomplete. It appears that “are” has been inadvertently omitted after “nanostructures.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6-9 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 6 recites “wherein second number of nanostructures stacked one over another over a second APT feature.” The recitation “second number of nanostructures” lacks proper antecedent basis. Claim 4, from which claim 6 ultimately depends, previously introduces “a second number of nanostructures.” It is unclear whether the “second number of nanostructures” recited in claim 6 is intended to refer to the previously recited “a second number of nanostructures.” For clarity and proper antecedent basis, “second number of nanostructures” should be amended to recite “the second number of nanostructures.”
Claims 7-9, because of their dependency on claim 6, these claims are also objected for the reasons set forth above with respect to claim 6.
Claim 17 recites “wherein second number of nanostructures stacked one over another over a second APT feature.” The recitation of “second number of nanostructures” lacks proper antecedent basis because it is unclear whether “second number of nanostructures” refers to “a second number of nanostructures” previously recited in claim 16. For clarity and proper antecedent basis, “second number of nanostructures” should be amended to recite “the second number of nanostructures.”
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Examiner conducted a comprehensive analysis of obviousness analysis including the Graham v. Deere analysis for each claim by (A) determining the scope and content of a reference claim relative to the claim in the application at issue; (B) determining the differences between the scope and content of the reference claim as determined in (A) and the claim in the application at issue; (C) determining the level of ordinary skill in the pertinent art; and (D) evaluation any objective indicia of nonobviousness.
The examiner has concluded that there is issue of double patenting rejection in the current application. This is because the claims in this application are deemed to be patentably does not distinct from any claims in a potential double patenting reference. Moreover, the examined application's claim is either anticipated or obvious over the reference claim(s).
Claims 1-8 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over U.S. Patent No. 11,710,737 (“Pat-737”) in view of Noh et al. (US 20200091152).
Regarding claim 1. Claim 1 of Pat-737 claims a semiconductor device comprising first and second transistors. The first transistor includes two first source/drain features, a first number of nanostructures stacked vertically one over another and extending lengthwise between the two first source/drain features, and a first dummy epitaxial feature disposed below each of the two first source/drain features. The second transistor includes two second source/drain features, a second number of nanostructures stacked vertically one over another and extending lengthwise between the two second source/drain features, and a second dummy epitaxial feature disposed below at least one of the two second source/drain features. Claim 1 of the Pat-737 further requires that the first number of nanostructures is smaller than the second number of nanostructures.
Thus, claim 1 of the Pat-737 claims first and second transistor structures having respective first and second source/drain features and respective first and second dummy epitaxial features disposed below the corresponding source/drain features.
But the claim 1 of the Pat-737 does not expressly recite (i) a substrate having a first region and a second region, with a first base fin in the first region and a second base fin in the second region, the first and second base fins extending lengthwise along a direction, or (ii) a height of the first source/drain feature being smaller than a height of the second source/drain feature.
However, Noh teaches a fin-based substrate arrangement suitable for implementing the first and second transistor structures of the Pat-737. Noh discloses a semiconductor substrate and a first fin-type pattern 149 formed as a portion of the substrate. See Noh [0017] and Fig. 2. As illustrated in Fig. 2, fin-type pattern 149 extends through the transistor structure and includes semiconductor base portions underlying the respective source/drain structures. In particular, a portion of fin-type pattern 149 directly underlies first source/drain region 151, while another portion of fin-type pattern 149 directly underlies second source/drain region 152.
Although Noh illustrates these semiconductor base portions as portions of fin-type pattern 149, it would have been obvious to one of ordinary skill in the art to implement the separate first and second transistor structures expressly claimed in claim 1 of the Pat-737 on respective first and second semiconductor base fins of the type taught by Noh. Providing respective transistor structures on respective semiconductor fins would have constituted a predictable implementation of the first and second transistor structures using Noh's known fin-based semiconductor architecture and would provide a semiconductor base structure underlying each respective transistor structure.
Further, implementing the respective first and second transistor structures on respective longitudinally extending semiconductor fins of the type taught by Noh would have resulted in a first base fin and a second base fin extending lengthwise along a common direction. The respective portions of the semiconductor substrate in which the first and second base fins are provided constitute the claimed first and second regions of the substrate. Instant claim 1 does not require any particular physical boundary, spacing, material difference, or other structural distinction between the recited first and second regions. Thus, the respective substrate portions containing the first and second base fins satisfy “a substrate having a first region and a second region,” “a first base fin in the first region,” and “a second base fin in the second region,” as recited in instant claim 1.
Noh further teaches the claimed relative source/drain-height relationship. Noh discloses first source/drain region 151 disposed between first and second gate structures G1 and G2. First source/drain region 151 passes through second and third wire patterns 142 and 143 and is disposed on first wire pattern 141. Noh further discloses second source/drain region 152 disposed between first and third gate structures G1 and G3, wherein second source/drain region 152 passes through first, second, and third wire patterns 141, 142, and 143.
Noh expressly teaches that bottom surface 151b of first source/drain region 151 is higher than bottom surface 152b of second source/drain region 152. Noh further defines a first depth d1 extending from the upper surface of first source/drain region 151 to bottom surface 151b and a second depth d2 extending from the upper surface of second source/drain region 152 to bottom surface 152b, and expressly teaches that d1 is smaller than d2. As illustrated in Fig. 2, d1 and d2 represent the respective vertical dimensions extending between the upper and bottom surfaces of source/drain regions 151 and 152. Accordingly, Noh teaches the claimed relative dimensional relationship in which a height of a first source/drain feature is smaller than a height of a second source/drain feature.
Thus, it would have been obvious to one of ordinary skill in the art to provide the first and second source/drain features of the semiconductor device claimed in claim 1 of the Pat-737 with the unequal vertical dimensions taught by Noh. Noh's first source/drain region 151 is associated with fewer vertically arranged wire patterns than second source/drain region 152: first source/drain region 151 passes through second and third wire patterns 142 and 143, whereas second source/drain region 152 passes through first through third wire patterns 141, 142, and 143. Noh correspondingly provides first source/drain region 151 with the smaller vertical dimension d1 and second source/drain region 152 with the larger vertical dimension d2.
One of ordinary skill in the art therefore would have recognized from Noh that source/drain features associated with different vertical channel configurations may be provided with correspondingly different vertical dimensions to accommodate the respective vertical extents of the associated channel structures. This modification is particularly applicable to claim 1 of the Pat-737 because that claim itself recites different first and second vertical channel configurations: a first number of vertically stacked nanostructures for the first transistor and a second number of vertically stacked nanostructures for the second transistor, expressly requiring that the first number is smaller than the second number. Thus, applying Noh's unequal source/drain vertical dimensions to the patented first and second transistor structures would have predictably resulted in the source/drain feature associated with the smaller first number of vertically stacked nanostructures having a smaller vertical height than the source/drain feature associated with the larger second number of vertically stacked nanostructures.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the first and second transistor structures claimed in claim 1 of the Pat-737 on respective first and second semiconductor base fins extending lengthwise along a direction in respective regions of a semiconductor substrate, using the fin-based substrate architecture taught by Noh, and to provide the respective first and second source/drain features with the unequal vertical dimensions taught by Noh, such that a height of the first source/drain feature is smaller than a height of the second source/drain feature.
The combination would therefore provide a substrate having first and second regions; respective first and second base fins in the first and second regions extending lengthwise along a direction; respective first and second dummy epitaxial features over the first and second base fins; respective first and second source/drain features over the first and second dummy epitaxial features; and a first source/drain feature having a height smaller than that of the second source/drain feature, as recited in instant claim 1.
Regarding claim 2, the claim 2 of Pat-737, through its dependency from claim 1, further recites that “a bottommost nanostructure of the second number of nanostructures is lower than a bottommost nanostructure of the first number of nanostructures.” Thus, claims 1 and 2 of the Pat-737 expressly claim first and second transistor structures having vertically offset first and second nanostructure stacks, wherein the second nanostructure stack extends to a lower vertical level than the first nanostructure stack.
Claim 1 of the Pat-737 further recites a first dummy epitaxial feature disposed below each of the first source/drain features associated with the first nanostructure stack and a second dummy epitaxial feature disposed below at least one of the second source/drain features associated with the second nanostructure stack. Although claims 1 and 2 of the Pat-737 do not expressly recite the relative vertical positions of the top surfaces of the first and second dummy epitaxial features, it would have been obvious to one of ordinary skill in the art to position the respective dummy epitaxial features at vertical levels corresponding to the different vertical levels of their associated nanostructure stacks.
In particular, because claim 2 of the Pat-737 expressly positions the bottommost nanostructure of the second nanostructure stack lower than the bottommost nanostructure of the first nanostructure stack, one of ordinary skill in the art would have found it obvious to correspondingly position the second dummy epitaxial feature associated with the lower second nanostructure stack at a lower vertical level than the first dummy epitaxial feature associated with the higher first nanostructure stack. Such an arrangement would predictably result in a top surface of the first dummy epitaxial layer being higher than a top surface of the second dummy epitaxial layer, as recited in instant claim 2.
This modification is further consistent with Noh's teaching of providing vertically differentiated semiconductor structures in accordance with different vertical channel configurations. Noh teaches that first source/drain region 151 is associated with fewer vertically arranged wire patterns than second source/drain region 152. Noh further teaches that first source/drain region 151 has a first vertical dimension d1 and second source/drain region 152 has a second vertical dimension d2, wherein d1 is smaller than d2. Noh therefore demonstrates that structures associated with different vertical channel configurations may predictably be provided at different vertical dimensions and levels to accommodate the respective channel configurations.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the vertically offset first and second nanostructure stacks claimed in claims 1 and 2 of Pat-737 with correspondingly vertically offset underlying dummy epitaxial features, such that a top surface of the first dummy epitaxial layer is higher than a top surface of the second dummy epitaxial layer, as recited in instant claim 2.
Regarding claim 3, Noh further teaches the relative base-fin top-surface relationship recited therein. As discussed above with respect to claim 1, Noh discloses a semiconductor substrate and a fin-type pattern 149 formed as a portion of the substrate. See Noh [0017] and Fig. 2. Fig. 2 illustrates a first semiconductor base-fin portion of fin-type pattern 149 directly underlying first source/drain region 151 and a second semiconductor base-fin portion of fin-type pattern 149 directly underlying second source/drain region 152.
As illustrated in Fig. 2, the top surface of the first base-fin portion underlying first source/drain region 151 is positioned at a higher vertical level than the top surface of the second base-fin portion underlying second source/drain region 152. Under the mapping discussed above with respect to instant claim 1, these respective semiconductor base-fin portions correspond to the claimed first and second base fins. Thus, Noh illustrates the additional limitation of instant claim 3 that “a top surface of the first base fin is higher than a top surface of the second base fin.”
Noh's illustrated fin-top relationship is further consistent with the vertically differentiated structure expressly described for source/drain regions 151 and 152. Noh states that bottom surface 151b of first source/drain region 151 is higher than bottom surface 152b of second source/drain region 152 relative to the upper surface of substrate 100. Accordingly, Noh teaches a fin-based transistor architecture having different vertical levels underlying the respective first and second source/drain configurations.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, when implementing the first and second transistor structures claimed in claim 1 of Pat-737 using the fin-based substrate architecture taught by Noh, to employ the relative base-fin configuration illustrated by Noh, thereby providing the first base fin with a top surface higher than the top surface of the second base fin. Such implementation would have been the predictable use of Noh's disclosed fin geometry in providing the respective semiconductor bases for the first and second transistor structures.
Regarding claim 4, claim 1 Pat-737 in view of Noh teaches the limitations of instant claim 1 as discussed above. Further, claim 1 of Pat-737 teaches the additional limitations of instant claim 4.
Specifically, claim 1 of the Pat-737 recites a first number of nanostructures that are stacked vertically one over another and a second number of nanostructures that are stacked vertically one over another, and further expressly recites that “the first number is smaller than the second number.” Thus, claim 1 of the Pat-737 expressly teaches first and second numbers of nanostructures, wherein the first number is smaller than the second number, as recited in instant claim 4.
Regarding claim 5, claim 1 of Pat-737 in view of Noh teaches the limitations of instant claim 1 as discussed above, and claim 1 of Pat-737 further teaches the limitations of instant claim 4 as discussed above. Further, Noh teaches the additional limitations of instant claim 5.
Specifically, instant claim 5 further requires that the first number is two and the second number is three.
Noh teaches a first transistor configuration having two vertically arranged channel members and a second transistor configuration having three vertically arranged channel members. In particular, Noh discloses that first source/drain region 151 passes through the second and third wire patterns 142 and 143 and is disposed on the first wire pattern 141, whereas second source/drain region 152 passes through the first, second, and third wire patterns 141, 142, and 143. Accordingly, Noh teaches a first source/drain/channel configuration involving two vertically arranged channel members 142 and 143, and a second source/drain/channel configuration involving three vertically arranged channel members 141, 142, and 143.
Claim 1 of the Pat-737 already expressly claims a first number of vertically stacked nanostructures and a second number of vertically stacked nanostructures, wherein the first number is smaller than the second number. Thus, Noh provides a specific implementation of the unequal channel-number relationship already claimed in the Pat-737, namely, two channel members for the first configuration and three channel members for the second configuration.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the first and second numbers of vertically stacked nanostructures claimed in claim 1 of the Pat-737 using the specific two-channel and three-channel configurations taught by Noh. Such a modification preserves the expressly claimed relationship that the first number is smaller than the second number while employing Noh's known specific channel-number configuration. The modification therefore would have predictably resulted in the first number being two and the second number being three, as recited in instant claim 5.
Regarding claim 6, claims 1 and 4–5 of Pat-737 in view of Noh teach the limitations of instant claim 1 as discussed above. Further, claims 1 and 4–5 of Pat-737 teach the additional limitations of instant claim 6.
Specifically, claim 1 of the Pat-737 recites a first number of nanostructures that are stacked vertically one over another and a second number of nanostructures that are stacked vertically one over another. Claim 5 of the Pat-737, through its dependency from claims 4 and 1, further recites a first anti-punch-through (APT) feature disposed below the first number of nanostructures and a second APT feature disposed below the second number of nanostructures.
Accordingly, the first number of nanostructures of the Pat-737 is stacked over the first APT feature, and the second number of nanostructures is stacked over the second APT feature, thereby teaching the additional limitations of instant claim 6 requiring the first number of nanostructures stacked over a first APT feature and the second number of nanostructures stacked over a second APT feature.
Regarding claim 7, claims 1 and 4–6 of Pat-737 in view of Noh teach the limitations of instant claim 1 as discussed above. Further, claims 1 and 4–6 of Pat-737 teach or render obvious the additional limitations of instant claim 7.
Specifically, claim 5 of the Pat-737, through its dependency from claims 4 and 1, recites a first APT feature disposed below the first number of nanostructures and a second APT feature disposed below the second number of nanostructures. Claim 1 further recites respective first and second dummy epitaxial features disposed below the respective source/drain features, and claim 6 expressly recites that the first APT feature is in direct contact with the first dummy epitaxial feature and the second APT feature is in direct contact with the second dummy epitaxial feature.
Thus, claims 1 and 4–6 of the Pat-737 establish the sequential vertical arrangement of the respective nanostructures, APT features, and dummy epitaxial features, as well as direct contact between each APT feature and its corresponding dummy epitaxial feature. In view of this arrangement, it would have been obvious to one of ordinary skill in the art for an upper sidewall portion of each APT feature that is in direct contact with the corresponding dummy epitaxial feature to interface that dummy epitaxial feature, thereby providing the claimed relationship in which sidewalls of the first and second APT features interface the first and second dummy epitaxial layers, respectively.
Such a configuration would have been a predictable geometrical implementation of the direct-contact relationship expressly claimed in claim 6 of the Pat-737 and would not represent a patentable distinction over the claimed arrangement.
Regarding claim 8, claims 1–5 and 7 of Pat-737 in view of Noh teach the limitations of instant claim 1 as discussed above. Further, claims 1–5 and 7 of Pat-737 teach or render obvious the additional limitations of instant claim 8.
Specifically, claim 5 of the Pat-737, through its dependency from claims 1 and 4, recites a first APT feature disposed below the first number of nanostructures and a second APT feature disposed below the second number of nanostructures. Claim 7 of the Pat-737 further recites that the second APT feature is lower than the first APT feature.
Thus, claims 1–5 and 7 of the Pat-737 teach first and second APT features arranged at different vertical levels, with the second APT feature positioned lower than the first APT feature. In view of this expressly claimed relative vertical arrangement, it would have been obvious to one of ordinary skill in the art to correspondingly position the bottommost surface of the second APT feature lower than the bottommost surface of the first APT feature, thereby resulting in the bottommost surface of the first APT feature being higher than the bottommost surface of the second APT feature, as recited in instant claim 8.
Such a configuration would have been a predictable geometrical implementation of the relative vertical positioning of the first and second APT features expressly claimed in claim 7 of the Pat-737.
Claims 18-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 11,710,737 “Pat-737”). Although the claims at issue are not identical, they are not patentably distinct from each other:
Regarding claim 18. Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-14 of Pat-737.
Claims 10-14 of Pat-737 claim a semiconductor structure that is not patentably distinct from the semiconductor structure presently recited in claim 18.
More particularly, claim 10 of Pat-737 recites a semiconductor structure comprising a first number of channel members disposed over a first fin structure, a first gate structure wrapping around each of the first number of channel members, a second number of channel members disposed over a second fin structure, a second gate structure wrapping around each of the second number of channel members, a dielectric fin disposed between the first gate structure and the second gate structure, and an isolation feature disposed between the first fin structure and the second fin structure. Claim 10 further recites that the second number is greater than the first number.
Claims 12-14 of Pat-737 further define the relative vertical arrangement associated with the dielectric fin, first and second fin structures, and isolation feature. In particular, claim 12 recites that first and second bottom surfaces of the dielectric fin comprise a step change. Claim 13 recites that a top surface of the first fin structure is higher than a top surface of the second fin structure, that the first bottom surface of the dielectric fin is coplanar with the top surface of the first fin structure, and that the second bottom surface of the dielectric fin is coplanar with the top surface of the second fin structure. Claim 14 further recites that the isolation feature comprises a first top surface and a second top surface lower than the first top surface.
Thus, claims 10-14 of Pat-737 collectively claim first and second fin structures having respective pluralities of channel members and respective gate structures, a dielectric fin between the gate structures, and an isolation feature between the fin structures having top surfaces at different vertical levels, thereby providing the stepped or stair-like top-surface configuration recited in present claim 18.
Present claim 18 recites substantially the same semiconductor structure, including a substrate, first and second fin structures over the substrate, an isolation feature disposed over the substrate and between the first and second fin structures, respective first and second numbers of channel members disposed over the respective fin structures, respective first and second gate structures wrapping around the channel members, and a dielectric fin disposed over the isolation feature and between the first and second gate structures. Present claim 18 further recites that the isolation feature comprises a stair-like top surface and that the first number is greater than the second number.
The recitation in present claim 18 that the “first number is greater than the second number,” rather than the recitation in claim 10 of Pat-737 that the “second number [is] greater than the first number,” does not render the presently claimed subject matter patentably distinct. The designations “first” and “second” are ordinal designations used to distinguish the two corresponding sets of structures. Neither present claim 18 nor claims 10-14 of Pat-737 recites a structural characteristic of the respective structures that requires a particular structure to retain the designation “first” rather than “second.”
Accordingly, the structures recited in claims 10-14 of Pat-737 may be mapped to present claim 18 by designating the second fin structure, second number of channel members, and second gate structure of the patented claims as the first fin structure, first number of channel members, and first gate structure, respectively, of present claim 18, and by correspondingly designating the first fin structure, first number of channel members, and first gate structure of the patented claims as the second fin structure, second number of channel members, and second gate structure, respectively, of present claim 18.
Upon this consistent interchange of the ordinal designations, the relationship in claim 10 of Pat-737 that the second number is greater than the first number corresponds to the relationship in present claim 18 that the first number is greater than the second number. The interchange does not alter the claimed semiconductor structure; it merely changes the nomenclature used to identify the two respective portions of the structure.
Further, the requirement of present claim 18 that the isolation feature comprise a “stair-like top surface” does not patentably distinguish the claimed structure from claims 10-14 of Pat-737. Claims 12-14 expressly establish different vertical levels associated with the first and second portions of the structure and, particularly, claim 14 expressly requires the isolation feature to have a first top surface and a second top surface lower than the first top surface. Such different top-surface levels define the stepped top-surface configuration encompassed by the “stair-like top surface” recited in present claim 18.
Therefore, the differences between present claim 18 and claims 10-14 of Pat-737 amount to an interchange of the ordinal designations “first” and “second” and terminology describing the stepped top surface of the isolation feature, rather than a patentably distinct structural arrangement.
Regarding claim 19. claim 19 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-14 of Pat-737. Although the claims at issue are not identical, they are not patentably distinct from each other.
As discussed above with respect to claim 18, claims 10-14 of Pat-737 claim the same underlying semiconductor structure recited in claim 18, with the respective “first” and “second” structures designated in reverse order. The ordinal designations “first” and “second” do not themselves impart a structural distinction to the respective fin structures, channel members, gate structures, or associated portions of the semiconductor structure.
Claim 19 depends from claim 18 and further recites that “a top surface of the first fin structure is lower than a top surface of the second fin structure.”
Claim 13 of Pat-737 recites that “a top surface of the first fin structure is higher than a top surface of the second fin structure.” This apparent difference does not patentably distinguish claim 19 because it results from the same interchange of the ordinal designations “first” and “second” discussed with respect to claim 18.
More particularly, when the second fin structure of claims 10-14 of Pat-737 is designated as the “first fin structure” of instant claims 18 and 19, and the first fin structure of claims 10-14 of Pat-737 is designated as the “second fin structure” of instant claims 18 and 19, the relationship recited in patented claim 13 that the top surface of the first fin structure is higher than the top surface of the second fin structure becomes, using the terminology of instant claim 19, a top surface of the first fin structure that is lower than a top surface of the second fin structure.
Significantly, this is the same consistent interchange of the first and second structures that accounts for the numerical relationship recited in claim 18. Claim 10 of Pat-737 recites that the second number of channel members is greater than the first number. Upon the same interchange of the first and second designations, the patented relationship corresponds to the limitation of instant claim 18 that the first number is greater than the second number. Likewise, patented claim 13's first-fin-higher-than-second-fin relationship corresponds to instant claim 19's first-fin-lower-than-second-fin relationship.
Thus, the limitations of instant claims 18 and 19 do not define a different structural arrangement from that claimed in claims 10-14 of Pat-737. Rather, the respective structures and their claimed relationships are maintained while the ordinal designations “first” and “second” are consistently interchanged.
Accordingly, the additional limitation of claim 19 does not render the claimed semiconductor structure patentably distinct from the subject matter claimed in claims 10-14 of Pat-737.
Allowable Subject Matter
Claims 11-15 are allowed. Furthermore, Claim 16 would be allowable if rewritten or otherwise amended to overcome the objection thereto. And Claim 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, The prior art of record fails to teach or render obvious the claimed semiconductor structure including, in combination:
a first source/drain feature disposed between two first dielectric fins along a second direction perpendicular to the first direction;
a second source/drain feature disposed between two second dielectric fins along the second direction; and
a height of the first source/drain feature being smaller than a height of the second source/drain feature.
Son et al. (US 20200303521; in the IDS on 7/24/24) teaches semiconductor structures including a substrate 102, fin-type active areas FA extending lengthwise along a first direction, dummy epitaxial layers 132, and source/drain features 134 disposed over the dummy epitaxial layers (Figs. 1 and 2A). However, Son does not teach or suggest the claimed combination in which the respective first and second source/drain features are each disposed between two respective dielectric fins along a second direction perpendicular to the first direction and the first source/drain feature has a smaller height than the second source/drain feature.
Noh et al. (US 20200091152) teaches source/drain features having different vertical dimensions, including source/drain features associated with different device regions. However, Noh does not cure the deficiency of Son because Noh does not teach or suggest the claimed arrangement of the first source/drain feature between two first dielectric fins and the second source/drain feature between two second dielectric fins along the second direction, in combination with the claimed relative source/drain heights.
Accordingly, the prior art of record, whether considered individually or in combination, fails to teach or render obvious the claimed arrangement wherein the first and second source/drain features are respectively disposed between two first dielectric fins and two second dielectric fins along the second direction perpendicular to the longitudinal direction of the base fins, in combination with the first source/drain feature having a smaller height than the second source/drain feature. For at least these reasons, claim 11 is considered allowable.
Claims 1-10 and 18-20 would be allowable if overcome the nonstatutory double patenting rejection. Furthermore, Claim 6 would be allowable if rewritten to overcome the objection and the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, Son et al. (US 20200303521) teaches a semiconductor structure including a substrate 102 having first and second regions, respective first and second base fins FA extending lengthwise along the same direction, respective dummy epitaxial layers 132 over the base fins, and respective source/drain features 134 over the dummy epitaxial layers (Figs. 1 and 2A; [0025], [0120]–[0121]). Figures 1 and 2A illustrate the corresponding plan-view and cross-sectional relationships of these structures.
Son, however, does not teach or suggest that a height of the first source/drain feature is smaller than a height of the second source/drain feature.
Noh et al. (US 20200091152) teaches source/drain features having different heights in different device regions, including first source/drain feature 151 in region I and second source/drain feature 254 in region II, wherein the first source/drain feature 151 has a smaller height than the second source/drain feature 254 (Fig. 2; [0031]).
Although Noh separately teaches source/drain features having different heights, the prior art of record does not provide sufficient teaching, suggestion, or reason for one of ordinary skill in the art to modify the corresponding first and second source/drain features 134 of Son to incorporate Noh's particular unequal-height source/drain configuration such that the first source/drain feature of Son has a smaller height than the second source/drain feature, as required by claim 1.
In particular, merely applying Noh's relative source/drain-height relationship to Son based on the fact that Noh discloses that relationship would require selection of the claimed relative configuration without a sufficient reason in the prior art for making that particular modification to Son. Accordingly, the examiner does not find that Son in view of Noh renders obvious the claimed combination, particularly the claimed arrangement wherein the first and second dummy epitaxial layers are respectively disposed over the first and second base fins, the first and second source/drain features are respectively disposed over those dummy epitaxial layers, and the height of the first source/drain feature is smaller than the height of the second source/drain feature. Accordingly, claim 1 is considered allowable over Son in view of Noh.
Regarding claim 18, Son et al. (US 20200303521; in the IDS on 7/24/24) teaches a semiconductor structure including a substrate 102 having fin-type active areas FA separated by device isolation layer 114, nanosheet stacks NSS including a plurality of vertically stacked nanosheets disposed over the fin-type active areas FA, and gate structures including gate lines 160 that surround the nanosheets. Son further teaches that the fin-type active areas extend in the X direction and that the gate lines extend in the Y direction across the fin-type active areas.
Noh et al. (US 20200091152) also teaches semiconductor structures employing fin structures and vertically arranged channel members, including configurations having different numbers of vertically arranged channel members in different device arrangements.
However, Son and Noh, whether considered individually or in combination, fail to teach or render obvious the particular combination recited in claim 18, including a dielectric fin disposed over an isolation feature and between the first and second gate structures, wherein the isolation feature has a stair-like top surface and the first number of channel members disposed over the first fin structure is greater than the second number of channel members disposed over the second fin structure.
Although individual aspects of vertically stacked channel members, gate-all-around structures, fin structures, and isolation structures were known in the art, the prior art of record does not provide sufficient teaching or reason to arrive at the claimed combination of the dielectric fin positioned over the stair-like isolation feature between the respective gate structures together with the claimed unequal numbers of channel members. Accordingly, claim 18 is considered allowable.
Conclusion
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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