DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed July 24, 2024.
Claims 1-20 are pending. Claims 1, 11 and 16 are independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on January 22, 2025 and November 7, 2025. These IDSs have been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,131,776. Although the claims at issue are not identical, they are not patentably distinct from each other because: application claims 1-20 are anticipated by 12,131,776 claims 1-20.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "the static random-access memory" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kitagawa et al. (U.S. 2013/0028011; hereinafter “Kitagawa”) in view of Izumi et al. (U.S. 2016/0111138; hereinafter “Izumi”)
Regarding independent claim 1, Kitagawa teaches a memory device (Fig. 38), comprising:
a static random-access memory (see page 16, par. 0185) including:
two cross-coupled inverters (Fig. 38: 310/320);
a first access transistor (Fig. 38: M5) having a first drain/source region connected to a bit line (Fig. 38: BL) or a bit line bar, and a second drain/source region (Fig. 38: M5 comprising a second drain/source region connected to 300a); and
a second access transistor (Fig. 38: M6) having a third drain/source region connected to another one of the bit line or the bit line bar (Fig. 38: /BL), and a fourth drain/source region connected to the two cross-coupled inverters (Fig. 38: 310/320); and
a non-volatile memory (Fig. 38: 300a) having a first end directly connected to the second drain/source region of the first access transistor (Fig. 38: M5) and a second end directly connected to the two cross-coupled inverters (Fig. 38: 310/320) and configured to store data (see page 17, par. 0189) and recall the data using the static random-access memory (see page 17, par. 0191), and
determine a state of the non-volatile memory the one of the bit line and the bit line bar is at the high voltage and one of the first access transistor and the second access transistor is biased on (see page 17, par. 0191).
However, Kitagawa is silent with respect to wherein to initialize a recall operation to recall the data one of the bit line and the bit line bar is at low voltage and another one of the bit line and the bit line bar is at high voltage and the first access transistor and the second access transistor are biased on.
Similar to Kitagawa, Izumi teaches a memory device (Fig. 1) comprising a static random-access memory (see page 3, par. 0081) including two cross-coupled inverters (Fig. 2: M1/M2 and M3/M4), first access transistor connected to a bit line (Fig. 2: M5 connected to BL) and a second access transistor connected to a bit line bar (Fig. 2: M6 connected to XBL).
Furthermore, Izumi teaches a recall operation to recall the data one of the bit line and the bit line bar is at low voltage (Fig. 34: inverted bit line XBL are at low level, see page 10, par. 0188) and another one of the bit line and the bit line bar is at high voltage (Fig. 34: bit line BL is at high voltage, see page 10, par. 0188) and the first access transistor and the second access transistor are biased on (Fig. 34 word line WL is at high level).
Since Izumi and Kitagawa are from the same field of endeavor, the teachings described by Izumi would have been recognized in the pertinent art of Kitagawa.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Izumi with the teachings of Kitagawa for the purpose of achieves power saving during an active period, see Izumi’s page 1, par. 0014.
Regarding claim 2, Kitagawa in combination with Izumi teaches the limitations with respect to claim 1.
Furthermore, Kitagawa teaches wherein the static random-access memory (see page 16, par. 0185) includes a six-transistor static random-access memory (Fig. 38: 250) that includes four transistors that form the two cross-coupled inverters (Fig. 38: 310 and 320) and two transistors, including the first access transistor and the second access transistor, that control access to the two cross-coupled inverters (Fig. 38: M5/M6).
Regarding claim 3, Kitagawa in combination with Izumi teaches the limitations with respect to claim 1.
Furthermore, Izumi teaches one or more logic gates (Fig. 33: 70, TA, TB, SWA and SWB) electrically coupled to the static random-access memory (Fig. 33: 11) and configured to perform a logic operation with the data from the static random-access memory (see page 10, par. 0179-0181).
Regarding claim 4, Kitagawa in combination with Izumi teaches the limitations with respect to claim 3.
Furthermore, Izumi teaches one or more logic gates are configured to receive an input signal and to perform the logic operation on the input signal and the data from the static random-access memory (Fig. 33: SA_E, TEST1_E and TEST2_E).
Regarding claim 5, Kitagawa in combination with Izumi teaches the limitations with respect to claim 3.
Furthermore, Kitagawa teaches wherein the one or more logic gates are configured to perform one or more logic functions of AND, OR, NOT, NAND, NOR, XOR, XNOR, and Buffer functions (Fig. 33: transmission gates SWA and SWB perform buffer operations. Further, sense amplifier 70 performs comparison operations between bit lines, see also page 3, par. 0070).
Regarding claim 6, Kitagawa in combination with Izumi teaches the limitations with respect to claim 1.
Furthermore, Kitagawa teaches wherein the non-volatile memory includes a resistive random-access memory (see page 16, par. 0185).
Regarding claim 7, Kitagawa in combination with Izumi teaches the limitations with respect to claim 1.
Furthermore, Kitagawa teaches wherein the non-volatile memory includes one or more of a resistive random-access memory, a magneto-resistive random-access memory, a ferroelectric random-access memory, and/or a phase-change random-access memory (see page 16, par. 0185).
Regarding claim 8, Kitagawa in combination with Izumi teaches the limitations with respect to claim 1.
Furthermore, Kitagawa teaches wherein the memory device is configured to operate in three modes including a static random-access memory mode (see page 17, par. 0187), a non-volatile memory mode (see page 17, par. 0188-0189), and a compute-in-memory mode (see page 17, par. 0190-0192).
Regarding claim 9, Kitagawa in combination with Izumi teaches the limitations with respect to claim 8.
Furthermore, Kitagawa teaches wherein the static random-access memory is configured to be written and read in the static random-access memory mode (see page 17, par. 0187).
Regarding claim 10, Kitagawa in combination with Izumi teaches the limitations with respect to claim 8.
Furthermore, Kitagawa teaches wherein the non-volatile memory is configured to be set, reset, and recalled using the static random-access memory in the non-volatile memory mode (see page 17, par. 0188-0189 and 0191).
Regarding independent claim 11, Kitagawa teaches a memory device (Fig. 38), comprising:
a static random-access memory cell (see page 16, par. 0185) including:
first and second cross-coupled inverters (Fig. 38: 310/320); and
first and second access transistors (Fig. 38: M5/M6) configured to connect the first and second cross-coupled inverters (Fig. 38: 310/320) to first and second bit lines (Fig. 38: BL and /BL); and
a non-volatile memory (Fig. 38: 300a) electrically connected in series between the first inverter (Fig. 38: 310) and the first access transistor (Fig. 38: M5) and configured to store data (see page 17, par. 0189) and recall the data using the static random-access memory cell (see page 17, par. 0191), and
determine a state of the non-volatile memory the first bit line is at the high voltage and the first access transistor is biased on (see page 17, par. 0191).
However, Kitagawa is silent with respect to wherein to initialize a recall operation to recall the data the first bit line is at a low voltage and the second bit line is at a high voltage and the first access transistor and the second access transistors are biased on.
Similar to Kitagawa, Izumi teaches a memory device (Fig. 1) comprising a static random-access memory (see page 3, par. 0081) including two cross-coupled inverters (Fig. 2: M1/M2 and M3/M4), first access transistor connected to a bit line (Fig. 2: M5 connected to BL) and a second access transistor connected to a bit line bar (Fig. 2: M6 connected to XBL).
Furthermore, Izumi teaches a recall operation to recall the data the first bit line is at a low voltage (Fig. 34: inverted bit line XBL are at low level, see page 10, par. 0188) and the second bit line is at a high voltage (Fig. 34: bit line BL is at high voltage, see page 10, par. 0188) and the first access transistor and the second access transistors are biased on (Fig. 34 word line WL is at high level).
Since Izumi and Kitagawa are from the same field of endeavor, the teachings described by Izumi would have been recognized in the pertinent art of Kitagawa.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Izumi with the teachings of Kitagawa for the purpose of achieves power saving during an active period, see Izumi’s page 1, par. 0014.
Regarding claim 12, Kitagawa in combination with Izumi teaches the limitations with respect to claim 11.
Furthermore, Izumi teaches one or more logic gates (Fig. 33: 70, TA, TB, SWA and SWB) electrically coupled to the static random-access memory (Fig. 33: 11) and wherein the one or more logic gates are configured to perform a logic operation using data from the static random-access memory (see page 10, par. 0179-0181).
Regarding claim 13, Kitagawa in combination with Izumi teaches the limitations with respect to claim 11.
Furthermore, Kitagawa teaches wherein the memory device is configured to operate in a static random-access memory mode (see page 17, par. 0187), a non-volatile memory mode (see page 17, par. 0188-0189), and a compute-in-memory mode (see page 17, par. 0190-0192).
Regarding claim 14, Kitagawa in combination with Izumi teaches the limitations with respect to claim 13.
Furthermore, Kitagawa teaches wherein the static random-access memory is configured to be written and read in the static random-access memory mode (see page 17, par. 0187).
Regarding claim 15, Kitagawa in combination with Izumi teaches the limitations with respect to claim 13.
Furthermore, Kitagawa teaches wherein the non-volatile memory is configured to be set, reset, and recalled using the static random-access memory in the non-volatile memory mode (see page 17, par. 0188-0189 and 0191).
Regarding independent claim 16, Kitagawa teaches a method of operation of a memory device (Fig. 38), the method comprising:
operating in a non-volatile memory mode in the memory device (see page 17, par. 0188-0189); and
operating in the non-volatile memory mode to set, reset, and recall data (see page 17, par. 0188-0189 and 0191) from a non-volatile memory (Fig. 38: 300a) electrically connected to two cross-coupled inverters (Fig. 38: 310/320) and one of two transistors (Fig. 38: M5/M6) that control access to the two cross-coupled inverters (Fig. 38: 310/320) in the static random-access memory (see page 16, par. 0185), wherein operating in the non-volatile memory mode comprises:
charging one of the bit line or the bit line bar to the high voltage and turning on one of the two transistors to determine a state of the non-volatile memory (see page 17, par. 0191).
However, Kitagawa is silent with respect to discharging one of a bit line or a bit line bar to a low voltage and charging the other one of the bit line or the bit line bar to a high voltage and turning one the two transistors to initialize a recall operation.
Izumi teaches discharging one of a bit line or a bit line bar to a low voltage (Fig. 34: inverted bit line XBL are at low level, see page 10, par. 0188) and charging the other one of the bit line or the bit line bar to a high voltage (Fig. 34: bit line BL is at high voltage, see page 10, par. 0188) and turning one the two transistors to initialize a recall operation (Fig. 34 word line WL is at high level).
Since Izumi and Kitagawa are from the same field of endeavor, the teachings described by Izumi would have been recognized in the pertinent art of Kitagawa.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Izumi with the teachings of Kitagawa for the purpose of achieves power saving during an active period, see Izumi’s page 1, par. 0014.
Regarding claim 17, Kitagawa in combination with Izumi teaches the limitations with respect to claim 16.
Kitagawa teaches operating in a static random-access memory mode (see page 17, par. 0187), wherein the operating in the static random-access memory mode includes:
discharging the bit line or the bit line bar to the low voltage and turning on the two transistors to write data into the static random-access memory (Fig. 40(b)).
Furthermore, Izumi teaches pre-charging the bit line and the bit line bar to the high voltage and turning one the two transistors to read data from the static random-access memory (see page 4, par. 0092-0093).
Regarding claim 18, Kitagawa in combination with Izumi teaches the limitations with respect to claim 16.
Furthermore, Kitagawa teaches wherein operating in the non-volatile memory mode comprises:
discharging the bit line and the bit line bar to the low voltage and turning on the two transistors to set the non-volatile memory to a first state (Fig. 40(a)); and
charging the bit line and the bit line bar to the high voltage and turning on the two transistors to reset the non-volatile memory to a second state (Fig. 40(c)).
Regarding claim 19, Kitagawa in combination with Izumi teaches the limitations with respect to claim 16.
Furthermore, Izumi teaches operating in a compute-in-memory mode, wherein operating in the compute-in memory mode comprises:
receiving, at logic gates (Fig. 33: 70, TA, TB, SWA and SWB), an input signal (Fig. 33: SA_E, TEST1_E and TEST2_E);
receiving, at the logic gates (Fig. 33: 70, TA, TB, SWA and SWB), the data from the static random-access memory (Fig. 33: data through bit lines BL and XBL); and
performing one or more logic functions on the input signal and the data (see page 10, par. 0179-0181).
Regarding claim 20, Kitagawa in combination with Izumi teaches the limitations with respect to claim 16.
Furthermore, Kitagawa teaches discharging the bit line to the low voltage and charging the bit line bar to the high voltage (“potential difference appearing between the bit lines BL and /BL, see page 17, par. 0191);
biasing on the two transistors to initialize a recall operation (“recalling operation,” see page 17, par. 0191);
charging the bit line to the high voltage (Fig. 41: bit line BL = “H”); and
biasing on one of the two transistors that are connected to the bit line to determine a state of the non-volatile memory (see page 17, par. 0191).
Conclusion
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825