DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The IDS filed on July 24th, 2024 has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Method for manufacturing a package device with optical pathway.
Claim Objections
Claims 2, 8, and 17 are objected to because of the following informalities:
In claim 2, line 2, “a portion of the bonding dielectric layer” should be --a first portion of the bonding dielectric layer-- since “a second portion of the bonding dielectric layer” recited in claim 2, line 3.
In claim 8, line 6, “a bonding dielectric layer” should be --a first bonding dielectric layer-- since claim 8 recites “a second bonding dielectric layer” on line 13.
In claim 8, line 8, “optically homogeneous material” should be --an optically homogeneous material--.
In claim 8, line “a bonding dielectric layer” should be --a first bonding dielectric layer-- since “a second bonding dielectric layer” recited in claim 8, line 13.
In claim 8, line 11, “metal bond pads” should be --first metal bond pads-- since “second metal bond pads” recited in claim 8, line 14.
In claim 17, lines 5-6, “an opening” should be --a first opening-- since “a second opening” is recited in claim 19, lines 3-4 and claim 20, line 3.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 8-11, and 15-18 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,899,242. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the claimed invention of the present application is encompassed by the scope of the claimed invention of U.S. Patent No. 11,899,242, see comparison table below.
Claims of present application
Claims of U.S. Patent No. 11,899,242
1. A method comprising: forming an optical feature on a top surface of an optical integrated circuit; forming an interconnect structure over the optical integrated circuit, the interconnect structure including a plurality of bond pads embedded in a topmost dielectric layer, wherein the interconnect structure includes a plurality of optical interfaces; removing a portion of the interconnect structure overlying the optical feature; and replacing the removed portion of the interconnect structure with an optically homogeneous material.
1. A method comprising; forming an optical feature on a first integrated circuit die; forming an interconnect structure overlying the first integrated circuit die, the interconnect structure including a plurality of stacked materials, wherein the interconnect structure imposes a first degree of optical interference on a light path extending to the optical feature; removing a portion of the interconnect structure to thereby form a gap in the interconnect structure overlying the optical feature; and filling the gap with a first bonding dielectric layer, the first bonding dielectric layer imposing a second degree of optical interference on the light path that is less than the first degree of optical interference, and fusion bonding the first bonding dielectric layer to a second bonding dielectric layer, the second bonding dielectric layer being a topmost layer of a second integrated circuit die.
2. The method of claim 1, further comprising depositing a bonding dielectric layer on the interconnect structure, a portion of the bonding dielectric layer forming the optically homogeneous material and a second portion of the bonding dielectric layer forming a bonding interface with a second bonding dielectric material.
2. The method of claim 1, further comprising: depositing a protective dielectric material over the first bonding dielectric layer, wherein the protective dielectric material encapsulates the second integrated circuit die.
3. The method of claim 1, further comprising: depositing a bonding dielectric layer on the interconnect structure; removing a portion of the bonding dielectric layer overlying the optical feature; and depositing a protective dielectric layer on the bonding dielectric layer, a portion of the protective dielectric layer forming the optically homogeneous material.
2. The method of claim 1, further comprising: depositing a protective dielectric material over the first bonding dielectric layer, wherein the protective dielectric material encapsulates the second integrated circuit die.
4. The method of claim 1, further comprising: depositing a bonding dielectric layer on the interconnect structure; depositing a protective dielectric layer on the bonding dielectric layer; and removing a portion of the protective dielectric layer overlying the optical feature and removing a portion of the bonding dielectric layer overlying the optical feature; and replacing the removed portion of the protective dielectric layer, the bonding dielectric layer, and the interconnect structure with the optically homogenous material.
. 2. The method of claim 1, further comprising: depositing a protective dielectric material over the first bonding dielectric layer, wherein the protective dielectric material encapsulates the second integrated circuit die.
8. A method comprising: forming an optical feature over a substrate; forming an interconnect structure overlying the substrate, the interconnect structure including a plurality of stacked materials, wherein the interconnect structure imposes a first degree of optical interference on a light path passing through the interconnect structure; depositing a bonding dielectric layer over the interconnect structure; forming a first gap in the interconnect structure, the first gap being aligned with the optical feature and filling the first gap with optically homogeneous material that imposes a second degree of optical interference on the light path less than the first degree of optical interference; forming metal bond pads in an upper surface of the bonding dielectric layer; bonding an electronic integrated circuit to the interconnect structure by dielectric-dielectric bonding the bonding dielectric to a second bonding dielectric layer of the electronic integrated circuit and by metal-metal bonding the metal bond pads to second metal bond pads of the electronic integrated circuit; and depositing a protective dielectric layer over the bonding dielectric layer.
1. A method comprising; forming an optical feature on a first integrated circuit die; forming an interconnect structure overlying the first integrated circuit die, the interconnect structure including a plurality of stacked materials, wherein the interconnect structure imposes a first degree of optical interference on a light path extending to the optical feature; removing a portion of the interconnect structure to thereby form a gap in the interconnect structure overlying the optical feature; and filling the gap with a first bonding dielectric layer, the first bonding dielectric layer imposing a second degree of optical interference on the light path that is less than the first degree of optical interference, and fusion bonding the first bonding dielectric layer to a second bonding dielectric layer, the second bonding dielectric layer being a topmost layer of a second integrated circuit die.
9. The method of claim 8 wherein the step of filling the first gap with an optically homogeneous material comprises filling the first gap with the bonding dielectric layer.
2. The method of claim 1, further comprising: depositing a protective dielectric material over the first bonding dielectric layer, wherein the protective dielectric material encapsulates the second integrated circuit die.
10. The method of claim 9, wherein the light path passes through the protective dielectric layer and the bonding dielectric layer, and further wherein the protective dielectric layer comprises a same material as the bonding dielectric layer.
4. The method of claim 2, wherein the first bonding dielectric layer and the protective dielectric material are formed of a same material composition.
11. The method of claim 10, wherein the protective dielectric layer is deposited using a same deposition process as used to deposit the bonding dielectric layer.
4. The method of claim 2, wherein the first bonding dielectric layer and the protective dielectric material are formed of a same material composition.
15. The method of claim 8, wherein the step of forming the first gap in the interconnect structure comprises forming a patterned mask layer over the interconnect structure and etching through the interconnect structure before the step of depositing the bonding dielectric layer over the interconnect structure.
2. The method of claim 1, further comprising: depositing a protective dielectric material over the first bonding dielectric layer, wherein the protective dielectric material encapsulates the second integrated circuit die.
16. The method of claim 8, wherein the step of forming the first gap in the interconnect structure comprises forming a patterned masking layer over the interconnect structure and the bonding dielectric layer and etching through the bonding dielectric layer and the interconnect structure before the step of bonding an electronic integrated circuit to the interconnect structure.
2. The method of claim 1, further comprising: depositing a protective dielectric material over the first bonding dielectric layer, wherein the protective dielectric material encapsulates the second integrated circuit die.
17. A method comprising: forming an optical feature on a top surface of an optical integrated circuit; forming an interconnect structure over the optical integrated circuit, the interconnect structure including a stack of metallization layers embedded within respective dielectric layer, wherein the interconnect structure includes a plurality of optical interfaces; removing a portion of the interconnect structure overlying the optical feature to form an opening over the optical feature; and filling the opening with an optically homogeneous material.
9. A method comprising: forming an optical feature on a first integrated circuit die; forming an interconnect structure overlying the first integrated circuit die, the interconnect structure including a plurality of stacked dielectric layers wherein optical interfaces exist between respective ones of the stacked dielectric layers; forming a gap in the interconnect structure by removing a portion of the interconnect structure overlying the optical feature; and filling the gap and covering the interconnect structure with a first bonding dielectric layer; fusion bonding a second integrated circuit die to the first bonding dielectric layer; and forming a protective layer over the first bonding dielectric layer and encapsulating the second integrated circuit die, wherein the protective layer and the first bonding dielectric layer form an optical path over the optical feature.
18. The method of claim 17, wherein the step of filling the opening with the optically homogeneous material comprises depositing a bonding dielectric layer in the opening, and further comprising fusion bonding an electronic integrated circuit to the bonding dielectric layer.
9. A method comprising: forming an optical feature on a first integrated circuit die; forming an interconnect structure overlying the first integrated circuit die, the interconnect structure including a plurality of stacked dielectric layers wherein optical interfaces exist between respective ones of the stacked dielectric layers; forming a gap in the interconnect structure by removing a portion of the interconnect structure overlying the optical feature; and filling the gap and covering the interconnect structure with a first bonding dielectric layer; fusion bonding a second integrated circuit die to the first bonding dielectric layer…
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 17, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (U.S. Pub. 2019/0004247).
In re claim 1, Huang discloses a method comprising: forming an optical feature 34 (grating coupler) on a top surface of an optical integrated circuit 10 (see paragraphs [0019], [0023] and fig. 1A); forming an interconnect structure 38 over the optical integrated circuit 10 (see paragraph [0023] and fig. 1A), the interconnect structure 38 including a plurality of bond pads 50 embedded in a topmost dielectric layer (see paragraphs [0025], [0026] and fig. 1A), wherein the interconnect structure 38 includes a plurality of optical interfaces (see paragraph [0026] and figs. 1A); removing a portion of the interconnect structure 38 overlying the optical feature 34 (see paragraph [0026] and figs. 1A, 1B, and 1G); and replacing the removed portion of the interconnect structure with an optically homogeneous material 90 (see paragraph [0045] and fig. 1G).
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In re claim 2, as applied to claim 1 above, Huang discloses wherein the method further comprising depositing a bonding dielectric layer 90 on the interconnect structure 38, a portion of the bonding dielectric layer 90 forming the optically homogeneous material and a second portion of the bonding dielectric layer forming a bonding interface with a second bonding dielectric material 74 (see paragraph [0030] and fig. 1G).
In re claim 3, as applied to claim 1 above, Huang discloses wherein the method further comprising: depositing a bonding dielectric layer 49 on the interconnect structure 38; removing a portion of the bonding dielectric layer 49 overlying the optical feature 34; and depositing a protective dielectric layer (74,90) on the bonding dielectric layer, a portion of the protective dielectric layer (74,90) forming the optically homogeneous material (see paragraph [0039] and fig. 1G).
In re claim 4, as applied to claim 1 above, Huang discloses wherein the method further comprising: depositing a bonding dielectric layer 49 on the interconnect structure; depositing a protective dielectric layer 74 on the bonding dielectric layer 49; and removing a portion of the protective dielectric layer 74 overlying the optical feature 34 and removing a portion of the bonding dielectric layer 49 overlying the optical feature 34; and replacing the removed portion of the protective dielectric layer 74, the bonding dielectric layer 49, and the interconnect structure 38 with the optically homogenous material 90 (see paragraphs [0039], [0045] and figs. 1A-1G).
In re claim 5, as applied to claim 4 above, Huang discloses wherein the step of replacing the removed portion of the protective dielectric layer 74, the bonding dielectric layer 49, and the interconnect structure 38 with the optically homogenous material 90 comprises depositing the optically homogeneous material 90 in a void formed by the steps of removing a portion of the interconnect structure 38, and removing a portion of the protective dielectric layer 74 overlying the optical feature 34 and removing a portion of the bonding dielectric layer 49 (see paragraphs [0039], [0045] and figs. 1A-1G).
In re claim 17, Huang discloses a method comprising: forming an optical feature 34 on a top surface of an optical integrated circuit 10 (see paragraph [0022] and figs. 1A-1G); forming an interconnect structure 38 over the optical integrated circuit 10, the interconnect structure 38 including a stack of metallization layers 44 embedded within respective dielectric layer 42 (see paragraph [0023] and figs. 1A-1G), wherein the interconnect structure 38 includes a plurality of optical interfaces (see paragraph [0025] and figs. 1A-G); removing a portion of the interconnect structure 38 overlying the optical feature 34 to form an opening (5A,52B) over the optical feature 34; and filling the opening with an optically homogeneous material 90 (see paragraphs [0026], [0045] and figs. 1A-G).
In re claim 19, as applied to claim 17 above, Huang discloses wherein the method further comprising forming a patterned bonding dielectric layer 49 over the interconnect structure 38, the patterned bonding dielectric layer 49 including a second opening over the optical feature 34, and filling the opening and the second opening by depositing a protective dielectric layer 90 on the bonding dielectric layer (see paragraphs [0025], [0045] and figs. 1A-1G).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-13, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (U.S. Pub. 2019/0004247) in view of Yuan et al. (U.S. Pub. 2017/0092626).
In re claim 8, Huang discloses a method comprising: forming an optical feature 34 over a substrate 2 (see paragraph [0022] and figs. 1A-1G); forming an interconnect structure 38 overlying the substrate 2, the interconnect structure 38 including a plurality of stacked materials, wherein the interconnect structure 38 imposes a first degree of optical interference on a light path passing through the interconnect structure 38 (see paragraph [0023] and figs. 1A-1G); depositing a bonding dielectric layer 49 over the interconnect structure 38; forming a first gap (52A,52B) in the interconnect structure 38, the first gap (52A,52B) being aligned with the optical feature 34 (see paragraph [0029] and figs. 1A-1G) and filling the first gap (52A,52B) with optically homogeneous material 90 that imposes a second degree of optical interference on the light path less than the first degree of optical interference (see paragraph [0045] and figs. 1A-1G, note that, the optically homogenous material 90 being a transparent adhesive material and thus inherently imposes a second degree of optical interference on the light path less than the first degree of optical interface of the interconnect structure of opaque material); forming metal bond pads 50 in an upper surface of the bonding dielectric layer 49; bonding an electronic integrated circuit 54 to the interconnect structure 38 (see paragraph [0018] and figs. 1A-1G); and depositing a protective dielectric layer 74 over the bonding dielectric layer 49 (see paragraph [0030] and figs. 1A-1G).
Huang is silent to wherein bonding an electronic integrated circuit to the interconnect structure by dielectric-dielectric bonding the bonding dielectric to a second bonding dielectric layer of the electronic integrated circuit and by metal-metal bonding the metal bond pads to second metal bond pads of the electronic integrated circuit.
However, Yuan discloses in a same field of endeavor, a method of manufacturing a semiconductor device, including, inter-alia, bonding an electronic integrated circuit to the interconnect structure by dielectric-dielectric bonding the bonding dielectric 220 to a second bonding dielectric layer 120 of the electronic integrated circuit and by metal-metal bonding the metal bond pads 223 to second metal bond pads 123 of the electronic integrated circuit (see paragraph [0047] and fig. 3B).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Yuan into the method of Huang in order to enable the step of bonding an electronic integrated circuit to the interconnect structure by dielectric-dielectric bonding the bonding dielectric to a second bonding dielectric layer of the electronic integrated circuit and by metal-metal bonding the metal bond pads to second metal bond pads of the electronic integrated circuit in Huang to be performed in order to improve integration density of the device structure (see paragraph [0002] of Yuan). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 9, as applied to claim 8 above, Huang in combination with Yuan discloses wherein the step of filling the first gap with an optically homogeneous material comprises filling the first gap with the bonding dielectric layer (see paragraphs [0025], [0045] and figs. 1A-1G of Huang).
In re claim 10, as applied to claim 9 above, Huang in combination with Yuan discloses wherein the light path passes through the protective dielectric layer and the bonding dielectric layer, and further wherein the protective dielectric layer comprises a same material as the bonding dielectric layer (see paragraphs [0025], [0049] and figs. 1A-1G). Note that, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In re claim 11, as applied to claim 10 above, Huang in combination with Yuan discloses wherein the protective dielectric layer is deposited using a same deposition process as used to deposit the bonding dielectric layer (see paragraphs [0025], [0032], [0045] and figs. 1A-1G of Huang).
In re claim 12, as applied to claim 11 above, Huang in combination with Yuan discloses wherein the step of depositing the bonding dielectric layer 49 occurs before the step of forming the gap in the interconnect structure 38, and further comprising forming a second gap, aligned to the first gap, in the bonding dielectric layer 49, and further wherein the step of filling the first gap with optically homogenous material comprises filling the first gap and the second gap with the protective dielectric layer 90 (see paragraphs [0025], [0049] and figs. 1A-1G of Huang).
In re claim 13, as applied to claim 12 above, Huang in combination with Yuan discloses wherein the step of depositing the bonding dielectric layer 46 occurs before the step of forming the first gap in the interconnect structure, 38 and further comprising: forming a second gap, aligned to the first gap, in the bonding dielectric layer 46; forming a third gap, aligned to the second gap, in the protective dielectric layer 49; and further wherein the step of filling the first gap with optically homogenous material comprises filling the first gap, the second gap, and the third gap with the optically homogenous material (see paragraphs [0025]. [0045] and figs. 1A-1G of Huang).
In re claim 15, as applied to claim 8 above, Huang in combination with Yuan discloses wherein the step of forming the first gap in the interconnect structure 38 comprises forming a patterned mask layer 46 over the interconnect structure 38 and etching through the interconnect structure 38 before the step of depositing the bonding dielectric layer 49 over the interconnect structure 38 (see paragraph [0025] and figs. 1A-1G of Huang).
In re claim 16, as applied to claim 8 above, Huang in combination with Yuan discloses wherein the step of forming the first gap in the interconnect structure 38 comprises forming a patterned masking layer 46 over the interconnect structure 38 and the bonding dielectric layer 49 and etching through the bonding dielectric layer 49 and the interconnect structure 38 before the step of bonding an electronic integrated circuit 54 to the interconnect structure 38 (see paragraphs [0025], [0039] and figs. 1A-1G of Huang).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (U.S. Pub. 2019/0004247) in view of Sandhu et al. (U.S. Pub. 2015/0192737).
In re claim 6, as applied to claim 5 above, Huang discloses wherein the step of replacing the removed portion of the protective dielectric layer 74, the bonding dielectric layer 49, and the interconnect structure 38 with the optically homogenous material comprises 90 (see paragraphs [0025], [0045] and figs. 1A-1G) but is silent to depositing an oxide material in the void.
However, Sandhu discloses in a same field of endeavor, a method of manufacturing a semiconductor device, including, inter-alia, depositing an oxide material 125 into the void (see paragraph [0020] and fig. 1).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Sandhu into the method of Huang in order to enable the step of depositing an oxide material into the void in Huang to be performed since it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (U.S. Pub. 2019/0004247) in view of Sandhu et al. (U.S. Pub. 2015/0192737), as applied to claim 6 above, and further in view of Yuan et al. (U.S. Pub. 2017/0092626).
In re claim 7, as applied to claim 6 above, Huang and Sandhu are silent to wherein the method further comprising: metal bonding the plurality of bond pads to corresponding bond pads of an electronic integrated circuit; and fusion bonding the bonding dielectric layer to a corresponding bonding dielectric layer of the electronic integrated circuit.
However, Yuan discloses in a same field of endeavor, a method of manufacturing a semiconductor device, including, inter-alia, wherein the method further comprising: metal bonding the plurality of bond pads to corresponding bond pads of an electronic integrated circuit; and fusion bonding the bonding dielectric layer to a corresponding bonding dielectric layer of the electronic integrated circuit (see paragraph [0047] and fig. 3B).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Yuan into the method of Huang in order to enable the step of metal bonding the plurality of bond pads to corresponding bond pads of an electronic integrated circuit; and fusion bonding the bonding dielectric layer to a corresponding bonding dielectric layer of the electronic integrated circuit in Huang to be performed in order to improve integration density of the device structure (see paragraph [0002] of Yuan).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (U.S. Pub. 2019/0004247) in view of Yuan et al. (U.S. Pub. 2017/0092626), as applied to claim 13 above and further in view of Sandhu et al. (U.S. Pub. 2015/0192737).
In re claim 14, as applied to claim 13 above, Huang and Yuan are silent to wherein the optically homogenous material comprises an oxide material.
However, Sandhu discloses in a same field of endeavor, a method of manufacturing a semiconductor device, including, wherein the optically homogenous material 125 comprises an oxide material (see paragraph [0020] and fig. 1).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Sandhu into the method of Huang in order to enable wherein the optically homogenous material comprises an oxide material in Huang to be formed since it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (U.S. Pub. 2019/0004247) in view of Yuan et al. (U.S. Pub. 2017/0092626).
In re claim 18, as applied to claim 17 above, Huang discloses wherein the step of filling the opening (52A,52B) with the optically homogeneous material 90 (see paragraph [0045] and figs. 1A-1G) but is silent to wherein depositing a bonding dielectric layer in the opening, and further comprising fusion bonding an electronic integrated circuit to the bonding dielectric layer.
However, Yuan discloses in a same field of endeavor, a method of manufacturing a semiconductor device, including, inter-alia, depositing a bonding dielectric layer in the opening, and further comprising fusion bonding an electronic integrated circuit to the bonding dielectric layer (see paragraph [0047] and fig. 3B).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Yuan into the method of Huang in order to enable the step of depositing a bonding dielectric layer in the opening, and further comprising fusion bonding an electronic integrated circuit to the bonding dielectric layer in Huang to be performed in order to improve integration density of the device structure (see paragraph [0002] of Yuan).
In re claim 20, as applied to claim 17 above, Huang discloses wherein the method further comprising: forming a patterned bonding dielectric layer 46 over the interconnect structure 38, the patterned bonding dielectric layer 46 including a second opening over the optical feature 34; forming a patterned protective dielectric layer 49 over the interconnect structure 38, the patterned protective dielectric layer 49 including a third opening over the optical feature 34, and filling the opening, the second opening, and the third opening with optically homogeneous material (see paragraphs [0025], [0045] and figs. 1A-1G) but is silent to fusion bonding an electronic integrated circuit to the patterned bonding dielectric layer.
However, Yuan discloses in a same field of endeavor, a method of manufacturing a semiconductor device, including, inter-alia, fusion bonding an electronic integrated circuit to the patterned bonding dielectric layer (see paragraph [0047] and fig. 3B).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Yuan into the method of Huang in order to enable the step of fusion bonding an electronic integrated circuit to the patterned bonding dielectric layer in Huang to be performed in order to improve integration density of the device structure (see paragraph [0002] of Yuan).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cai et al. (U.S. Pub. 2016/0276807) discloses a method including, inter-alia, removing a portion of the dielectric waveguide material stack (22,24,26) overlying the substrate to form a gap 54; and replacing the removed portion of the dielectric waveguide material stack (22,24,26) with a material (56,58,62,64,66) (see paragraphs [0076], [0077], [0079], [0081] and figs. 7-11).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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