Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. US 10,923,413 B2 to Delacruz. Although the claims at issue are not identical, they are not patentably distinct from each other because the parent patent renders obvious the instant application.
Regarding independent claim 2: Delacruz teaches *(e.g., Claims 11-17) an integrated circuit (IC) device, comprising:
a host die; and
a chiplet directly bonded to the host die, the chiplet comprising:
a circuitry layer formed over a chiplet substrate and comprising active circuitry for serializing or deserializing signals signal received by the circuitry layer, one or more keepout zones laterally surrounded by the active circuitry, the one or more keepout zones defining spaces exclusive of the active circuitry, and
a plurality of surface interconnects formed over the one or more keepout zones at a surface of the chiplet facing away from the host die,
the surface interconnects comprising receive interconnects for receiving signals signal to be serialized or deserialized by the active circuitry and transmit interconnects for transmitting signals signal serialized or deserialized by the active circuitry (Claim 15).
Regarding claim 3: Delacruz teaches the claim limitation of the IC device of claim 2, on which this claim depends,
wherein the chiplet is directly bonded to the host die without an intervening redistribution layer therebetween (Claim 13).
Regarding claim 4: Delacruz teaches the claim limitation of the IC device of claim 2, on which this claim depends, wherein the circuitry layer faces the host die (Claim 12).
Regarding claim 5: Delacruz teaches the claim limitation of the IC device of claim 4, on which this claim depends,
wherein the chiplet is hybrid direct bonded to the host die without an intervening material therebetween (Claim 17).
Regarding claim 6: Delacruz teaches the claim limitation of the IC device of claim 2, on which this claim depends, wherein the circuitry layer faces away from the host die (Claim 11).
Regarding claim 7: Delacruz teaches the claim limitation of the IC device of claim 6, on which this claim depends,
wherein the chiplet further comprises one or more through-hole interconnects extending vertically through the chiplet substrate and electrically connected to the host die (Claim 15).
Regarding claim 8: Delacruz teaches the claim limitation of the IC device of claim 7, on which this claim depends,
wherein the through-hole interconnects extend further through the keepout zones in a vertical direction to contact the surface interconnects (Claim 16).
Regarding claim 9: Delacruz teaches the claim limitation of the IC device of claim 2, on which this claim depends,
wherein the surface interconnects include one or more of a bump, a pad and a pillar (Claim 16).
Regarding claim 11: Delacruz teaches the claim limitation of the IC device of claim 2, on which this claim depends,
further comprising a memory chiplet bonded to the host die (Claim 11).
Regarding claim 12: Delacruz teaches the claim limitation of the IC device of claim 2, on which this claim depends,
wherein the surface interconnects further comprises a power interconnect (Claim 15).
Regarding independent claim 2: Delacruz teaches (e.g., Claims 1-10) an integrated circuit (IC) device, comprising:
a host die; and
a chiplet directly bonded to the host die, the chiplet comprising:
a circuitry layer formed over a chiplet substrate and comprising active circuitry for serializing or deserializing signals signal received by the circuitry layer, one or more keepout zones laterally surrounded by the active circuitry, the one or more keepout zones defining spaces exclusive of the active circuitry, and
a plurality of surface interconnects formed over the one or more keepout zones at a surface of the chiplet facing away from the host die,
the surface interconnects comprising receive interconnects for receiving signals signal to be serialized or deserialized by the active circuitry and transmit interconnects for transmitting signals signal serialized or deserialized by the active circuitry (Claim 10).
Regarding claim 10: Delacruz teaches the claim limitation of the IC device of claim 2, on which this claim depends,
wherein the surface interconnects are electrically connected to an external device selected from the group consisting of a system on chip, a processor, a graphics processor, a neural network and a microcontroller (Claim 10).
Regarding independent claim 13: Delacruz teaches (e.g., Claims 1-10) an integrated circuit (IC) device, comprising:
a host die; and
a chiplet directly bonded to the host die, the chiplet comprising:
a circuitry layer formed over a chiplet substrate and comprising active circuitry for serializing or deserializing signals signal received by the circuitry layer,
one or more keepout zones laterally surrounded by the active circuitry, the one or more keepout zones defining spaces exclusive of the active circuitry,
a plurality of surface interconnects formed over the one or more keepout zones at a surface of the chiplet facing away from the host die, andone or more through-hole interconnects formed in the one or more keepout zones and vertically extending through the chiplet in a vertical direction,
wherein some of the through-hole interconnects electrically connect the surface interconnects and the host substrate (Claim 4).
Regarding claim 14: Delacruz teaches the claim limitation of the IC device of claim 13, on which this claim depends,
wherein the surface interconnects comprise receive interconnects for receiving signals signal to be serialized or deserialized by the active circuitry and transmit interconnects for transmitting signals signal serialized or deserialized by the active circuitry (Claim 10).
Regarding claim 15: Delacruz teaches the claim limitation of the IC device of claim 13, on which this claim depends,
further comprising a second layer device disposed over the chiplet and electrically connected to the one or more surface interconnects (Claim 10).
Regarding claim 16: Delacruz teaches the claim limitation of the IC device of claim 15, on which this claim depends,
wherein the second layer device is selected from the group consisting of a system on chip, a processor, a graphics processor, a neural network and a microcontroller (Claim 10).
Regarding independent claim 13: Delacruz teaches (e.g., Claims 11-17) an integrated circuit (IC) device, comprising:
a host die; and
a chiplet directly bonded to the host die, the chiplet comprising:
a circuitry layer formed over a chiplet substrate and comprising active circuitry for serializing or deserializing signals signal received by the circuitry layer,
one or more keepout zones laterally surrounded by the active circuitry, the one or more keepout zones defining spaces exclusive of the active circuitry,
a plurality of surface interconnects formed over the one or more keepout zones at a surface of the chiplet facing away from the host die, and one or more through-hole interconnects formed in the one or more keepout zones and vertically extending through the chiplet in a vertical direction,
wherein some of the through-hole interconnects electrically connect the surface interconnects and the host substrate (Claim 16).
Regarding claim 17: Delacruz teaches the claim limitation of the IC device of claim 13, on which this claim depends,
wherein the chiplet is directly bonded to the host die without an intervening redistribution layer therebetween (Claim 13).
Regarding claim 18: Delacruz teaches the claim limitation of the IC device of claim 13, on which this claim depends,
wherein the circuitry layer faces the host die (Claim 12).
Regarding claim 19: Delacruz teaches the claim limitation of the IC device of claim 19, on which this claim depends,
wherein the chiplet is hybrid direct bonded to the host substrate without an intervening material therebetween (Claim 13).
Regarding claim 20: Delacruz teaches the claim limitation of the IC device of claim 19, on which this claim depends,
wherein the circuitry layer faces away from the host die (Claim 13).
Regarding claim 21: Delacruz teaches the claim limitation of the IC device of claim 13, on which this claim depends,
wherein the surface interconnects include one or more of a bump, a pad and a pillar (Claim 15).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
Prosecution Insights