Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. Chen et al. US 10,763,365 B2 to Chen et al., hereinafter Chen365.
Claims 1-20 are similarly rejected by Chen et al., hereinafter Chen687 US 11,495,687 B2 and Chen et al., hereinafter Chen132, US 12,113,132 B2
Although the claims at issue are not identical, they are not patentably distinct from each other because the parent patent renders obvious the current applicant.
Chen et al. US 11495687 B2 is considered tied to the Double Patenting Rejection, although not explicitly used in this rejection.
Regarding independent claim 1: Chen365 teaches (e.g., Claims 1-7 and 16) a semiconductor device, comprising:
a substrate;
a vertical structure protruding from the substrate;
a conductive rail disposed adjacent to the vertical structure;
a dielectric layer disposed between the conductive rail and the substrate;
a semiconductor layer disposed between the conductive rail and the dielectric layer; and a source/drain region disposed on the vertical structure and the conductive rail (Claim 1).
Regarding claim 2: Chen365 teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the source/drain region is in contact with a top surface of the conductive rail (Claim 2).
Regarding claim 3: Chen365 teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the vertical structure comprises a fin structure (Claim 1).
Regarding claim 4: Chen365 teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the semiconductor layer comprises a silicon layer (Claim 1).
Regarding claim 5: Chen365 teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends, further comprising
a gate structure disposed adjacent to the source/drain region and in contact with a top surface of the conductive rail (Claim 4).
Regarding claim 6: Chen365 teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
further comprising another dielectric layer disposed between the source/drain region and the conductive rail (Claim 6).
Regarding claim 7: Chen365 teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
further comprising: another dielectric layer disposed on portions of the conductive rail that are uncovered by the source/drain region; and a gate structure disposed on the other dielectric layer and on a portion of the vertical structure protruding above the other dielectric layer (Claim 7).
Regarding claim 10: Chen365 teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends, further comprising:
another conductive rail disposed on the substrate and in parallel to the conductive rail; a first gate structure disposed on and in contact with the conductive rail; and a second gate structure disposed on and electrically isolated from the other conductive rail (Claim 5).
Claims 8-9 and 16 are similarly rejected by Chen et al., hereinafter Chen687 US 11,495,687 B2 and Chen et al., hereinafter Chen132, US 12,113,132 B2 in view of US 2015/0137271 A1 to Cai et al.
Regarding claim 8: Chen365 teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends.
Chen365 does not expressly teach that the device further comprises
a nitride layer disposed on a top surface of the vertical structure.
Cai teaches (e.g., Figs. 2A-2H) a device comprising a vertical structure ([0035], [0040] and [0046]: 106);
Cai further teaches that the device comprises a nitride layer ([0040]: e.g., titanium nitride) disposed on a top surface of the vertical structure ([0035], [0040] and [0046]: 106).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Chen, the nitride layer disposed on a top surface of the vertical structure, as taught by Cai, for the benefits of increasing the precision of the transistor’s threshold voltage.
Regarding claim 9: Chen365 and Cai teach the claim limitation of the semiconductor device of claim 8, on which this claim depends, further comprising
a gate structure (Cai: [0044]: 132) disposed on the nitride layer and sidewalls of the vertical structure (Cai: 106).
Regarding claim 16: Chen365 teaches the claim limitation of the semiconductor device of claim 11, on which this claim depends.
Chen365 does not expressly teach that the device further comprises
a nitride layer disposed on a top surface of the vertical structure.
Cai teaches (e.g., Figs. 2A-2H) a device comprising a vertical structure ([0035], [0040] and [0046]: 106);
Cai further teaches that the device comprises a nitride layer ([0040]: e.g., titanium nitride) disposed on a top surface of the vertical structure ([0035], [0040] and [0046]: 106).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Chen, the nitride layer disposed on a top surface of the vertical structure, as taught by Cai, for the benefits of increasing the precision of the transistor’s threshold voltage.
Regarding independent claim 11: Chen365 teaches (e.g., Claims 8-12) a semiconductor device, comprising:
a substrate; a fin structure disposed on the substrate;
a conductive rail disposed adjacent to the fin structure;
a metal-based layer disposed between the conductive rail and the substrate; and a gate structure disposed on the fin structure and the conductive rail (Claim 8).
Regarding claim 12: Chen365 teaches the claim limitation of the semiconductor device of claim 11, on which this claim depends,
wherein the gate structure is in contact with a top surface of the conductive rail (Claim 8).
Regarding claim 14: Chen365 teaches the claim limitation of the semiconductor device of claim 11, on which this claim depends, further comprising
a source/drain region disposed on and in contact with a top surface of the conductive rail (Claim 8).
Regarding claim 15: Chen365 teaches the claim limitation of the semiconductor device of claim 11, on which this claim depends, further comprising
a spacer disposed between the fin structure and the conductive rail (Claim 10).
Claim 13 is similarly rejected as claim 11 by Chen et al., hereinafter Chen687 US 11,495,687 B2 and Chen et al., hereinafter Chen132, US 12,113,132 B2 in view of US 2018/0294267 A1 to Licausi et al.
Regarding claim 13: Chen365 teaches the claim limitation of the semiconductor device of claim 11, on which this claim depends
Chen365 does not expressly teach that the metal-based layer comprises a tungsten layer, a cobalt layer, or a titanium nitride layer.
Licausi teaches (e.g., Figs. 10-12) a device comprising a metal-based layer ([0041]-[0043]: 46);
Licause further teaches that the metal-based layer comprises a tungsten layer, a cobalt layer, or a titanium nitride layer ([0041]-[0043]: 46 comprising titanium nitride, TiN).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Chen365, the metal-based layer comprising a titanium nitride layer, as taught by Licause, for the benefits of increasing improving the quality of the metal layer by using the titanium nitride as a seed layer; in addition, the titanium nitride layer is used as metal diffusion blocker; thus, improving the reliability of the interconnect structure.
Claims 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. Chen et al. US 12,113,132 B2 to Chen et al., hereinafter Chen132.
Regarding independent claim 17: Chen132 teaches (e.g., Claims 1-10) a method, comprising:
forming a fin structure on a substrate;
forming a seed layer on the substrate; forming a conductive rail on the seed layer; depositing a dielectric layer on the conductive rail;
etching a first portion of the dielectric layer to expose a first portion of the conductive rail, while covering a second portion of the conductive rail with a second portion of the dielectric layer; and forming a source/drain region on the fin structure and the first portion of the conductive rail (Claim 1).
Regarding claim 18: Chen132 teaches the claim limitation of the method of claim 17, on which this claim depends, further comprising
forming another source/drain on the fin structure and the second portion of the dielectric layer (Claim 9).
Regarding claim 19: Chen132 teaches the claim limitation of the method of claim 17, on which this claim depends,
wherein forming the seed layer comprises forming a semiconductor layer or a metal layer (Claim 4).
Regarding claim 20: Chen132 teaches the claim limitation of the method of claim 17, on which this claim depends, further comprising:
forming a polysilicon structure on a third portion of the dielectric layer; removing the polysilicon structure; etching the third portion of the dielectric layer to expose a third portion of the conductive rail; and forming a gate structure on the third portion of the conductive rail (Claim 6).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-13 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Licausi et al. (US 2018/0294267 A1).
Regarding independent claim 11: Licausi teaches (e.g., Figs. 1-13) a semiconductor device, comprising:
a substrate ([0026]: 18);
a fin structure ([0037]: 36) disposed on the substrate;
a conductive rail ([0041]-[0043]: 48) disposed adjacent to the fin structure;
a metal-based layer ([0041]-[0043]: 46) disposed between the conductive rail and the substrate; and
a gate structure ([0046]: 56) disposed on the fin structure and the conductive rail (48).
Regarding claim 12: Licausi teaches the claim limitation of the semiconductor device of claim 11, on which this claim depends,
wherein the gate structure (56) is in contact with a top surface of the conductive rail (48; no direct contact is required to meet the claim limitation requirement).
Regarding claim 13: Licausi teaches the claim limitation of the semiconductor device of claim 11, on which this claim depends, the metal-based layer ([0041]-[0043]: 46), comprises a tungsten layer, a cobalt layer, or a titanium nitride layer ([0041]-[0043]: 46 comprising titanium nitride, TiN).
Regarding claim 15: Licausi teaches the claim limitation of the semiconductor device of claim 11, on which this claim depends, further comprising
a spacer ([0038]: 40) disposed between the fin structure and the conductive rail (48).
Allowable Subject Matter
Claims 1-10 and 17-20 would be allowable if the double patenting rejection and all application rejections including art rejection are overcome.
In addition, claims 11-13 and 15 are rejected with art rejection; this rejection must also be overcome for the whole application to be allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HERVE-LOUIS Y ASSOUMAN/Examiner, Art Unit 2812
Prosecution Insights