DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/5/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-5, 8-9 and 12-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 6-13 and 16 of U.S. Patent No. 12,101,926. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 1, Pat '926 discloses, in claims 1 and 2, a device, comprising: a substrate; a first nanostructure over the substrate, including a semiconductor having a first resistance; a second nanostructure over the substrate, offset laterally from the first nanostructure, including a conductor having a second resistance lower than the first resistance; a first gate structure over and wrapped around the first nanostructure; and a second gate structure over and wrapped around the second nanostructure (all limitations are the same with the limitations recited in claim 1 of Pat '926);
wherein: the first nanostructure includes dopants in the semiconductor at a first doping concentration; the conductor of the second nanostructure includes the semiconductor and the dopants at a second doping concentration; and a ratio of the second doping concentration to the first doping concentration is at least about 100 (all limitations are the same with the limitations recited in claim 2 of Pat '926).
Regarding claim 2, Pat '926 discloses the device of claim 1 as described above.
Pat '926 further discloses, in claim 3, the dopants comprise boron, aluminum, gallium, indium, or a combination thereof (all limitations are the same with the limitations recited in claim 3 of Pat '926).
Regarding claim 3, Pat '926 discloses the device of claim 1 as described above.
Pat '926 does not explicitly disclose the first nanostructure includes dopants in the semiconductor at a doping concentration in a range of about 1016 atoms/cm3 to about 1021 atoms/cm3.
Pat '926 teaches, in claim 9, the first nanostructure includes dopants in the semiconductor at a doping concentration in a range of about 1016 atoms/cm3 to about 1021 atoms/cm3 ("the first channel comprises a semiconductor doped at a doping concentration in a range of about 1016 atoms/cm3 to about 1021 atoms/cm3", in claim 9 of Pat '926, is interpreted as the same limitation), for the purpose of providing 3D GAA capacitance devices to increase device density.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claims 1 and 2 of Pat '926 to have the first nanostructure including dopants in the semiconductor at a doping concentration in a range of about 1016 atoms/cm3 to about 1021 atoms/cm3, as taught by claim 9 of Pat '926, for the purpose of providing 3D GAA capacitance devices to increase device density.
Regarding claim 4, Pat '926 discloses the device of claim 1 as described above.
The claimed limitation of "the dopants are introduced into the first and second nanostructures by solid phase diffusion (SPD)" has not patentable weight because it is interpreted as product-by-process.
Regarding claim 5, Pat '926 discloses the device of claim 1 as described above.
Pat '926 further discloses, in claim 6, the first nanostructure is a nanosheet or nanowire of a field effect transistor; and the second nanostructure is a nanosheet or nanowire of an integrated capacitor (all limitations are the same with the limitations recited in claim 6 of Pat '926).
Regarding claim 8, Pat '926 discloses the device of claim 1 as described above.
The claimed limitation of "the first nanostructure and the second nanostructure are each formed by epitaxial growth" has not patentable weight because it is interpreted as product-by-process.
Regarding claim 9, Pat '926 discloses the device of claim 1 as described above.
Pat '926 further discloses, in claim 7, a first source/drain in contact with the first and second nanostructures; a first contact over and contacting a first side of the first source/drain; and a backside via under and contacting a second side of the first source/drain that is opposite the first side (all limitations are the same with the limitations recited in claim 7 of Pat '926).
Regarding claim 12, Pat '926 discloses, in claim 8, a device, comprising: a first die including a first transistor, the first transistor comprising: a first source/drain; a second source/drain; a first channel having a first end contacting the first source/drain and a second end contacting the second source/drain; and a backside via contacting the first source/drain; and a second die bonded to the first die, the second die comprising: a second source/drain electrically connected to the backside via ("a first capacitor of a second die, the first capacitor including: a first source/drain; a second source/drain; a first channel having a first end contacting the first source/drain, and a second end contacting the second source/drain; and a first contact over and contacting the first source/drain; and a first transistor of a first die bonded to the second die, the first transistor overlying the first capacitor, the first transistor including: a third source/drain; a fourth source/drain; a second channel having a first end contacting the third source/drain, and a second end contacting the fourth source/drain; and a backside via contacting the third source/drain, and electrically connected to the first source/drain", in claim 8 of Pat '926, is interpreted as the same limitation).
Regarding claim 13, Pat '926 discloses the device of claim 12 as described above.
Pat '926 further discloses, in claim 9, the first channel comprises a semiconductor doped at a doping concentration in a range of about 1016 atoms/cm3 to about 1021 atoms/cm3 (all limitations are the same with the limitations recited in claim 9 of Pat '926).
Regarding claim 14, Pat '926 discloses the device of claim 12 as described above.
Pat '926 further discloses, in claim 9, the first channel comprises a metal nitride (all limitations are the same with the limitations recited in claim 9 of Pat '926).
Regarding claim 15, Pat '926 discloses the device of claim 12 as described above.
Pat '926 further discloses, in claim 11, a second transistor of the second die; and a third transistor of the first die; wherein the third transistor overlies the second transistor, and a third source/drain of the third transistor is electrically connected to a fourth source/drain of the second transistor by at least one metal-to-metal bond at an interface of the first die and the second die ("a second transistor of the second die; and a third transistor of the first die; wherein the third transistor overlies the second transistor, and a fifth source/drain of the third transistor is electrically connected to a sixth source/drain of the second transistor by at least one metal-to-metal bond at an interface of the first die and the second die", in claim 11 of Pat '926, is interpreted as the same limitation).
Regarding claim 16, Pat '926 discloses the device of claim 15 as described above.
Pat '926 further discloses, in claim 12, a second channel of the second transistor has a doping concentration less than about 1013 atoms/cm3 ("a third channel of the second transistor has a doping concentration less than about 1013 atoms/cm3", in claim 12 of Pat '926, is interpreted as the same limitation).
Regarding claim 17, Pat '926 discloses the device of claim 12 as described above.
Pat '926 further discloses, in claim 13, the backside via is separated from the second source/drain by a buffer layer ("the backside via is separated from the fourth source/drain by a buffer layer", in claim 13 of Pat '926, is interpreted as the same limitation).
Regarding claim 18, Pat '926 discloses, in claims 1 and 2, a method, comprising: forming a first nanostructure and a second nanostructure over a substrate, the second nanostructure offset laterally from the first nanostructure; doping the first nanostructure at a first doping concentration; doping the second nanostructure at a second doping concentration, wherein a ratio of the second doping concentration to the first doping concentration is at least about 100; forming a first gate structure over and wrapped around the first nanostructure; and forming a second gate structure over and wrapped around the second nanostructure ("a substrate; a first nanostructure over the substrate, including a semiconductor having a first resistance; a second nanostructure over the substrate, offset laterally from the first nanostructure, including a conductor having a second resistance lower than the first resistance, the second resistance being less than about 100 ohms/square; a first gate structure over and wrapped around the first nanostructure; and a second gate structure over and wrapped around the second nanostructure" and “the first nanostructure includes dopants in the semiconductor at a first doping concentration; the conductor of the second nanostructure includes the semiconductor and the dopants at a second doping concentration; and a ratio of the second doping concentration to the first doping concentration is at least about 100”, in claims 1 and 2 of Pat '926, are interpreted as the same limitation).
Regarding claim 19, Pat '926 discloses the method of claim 18 as described above.
Pat '926 does not explicitly disclose doping semiconductor layers of the second nanostructure to a dopant concentration between about 1016 atoms/cm3 to about 1021 atoms/cm3.
Pat '926 teaches, in claim 9, doping semiconductor layers of the second nanostructure to a dopant concentration between about 1016 atoms/cm3 to about 1021 atoms/cm3 ("the first channel comprises a semiconductor doped at a doping concentration in a range of about 1016 atoms/cm3 to about 1021 atoms/cm3", in claim 9 of Pat '926, is interpreted as the same limitation), for the purpose of providing 3D GAA capacitance devices to increase device density.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in claims 1 and 2 of Pat '926 to have the doping semiconductor layers of the second nanostructure to a dopant concentration between about 1016 atoms/cm3 to about 1021 atoms/cm3, as taught by claim 9 of Pat '926, for the purpose of providing 3D GAA capacitance devices to increase device density.
Regarding claim 20, Pat '926 discloses the method of claim 18 as described above.
Pat '926 does not explicitly disclose the doping is by a solid phase diffusion process.
Pat '926 teaches, in claim 16, the doping is by a solid phase diffusion process (all limitations are the same with the limitations recited in claim 16 of Pat '926), for the purpose of providing 3D GAA capacitance devices to increase device density.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in claims 1 and 2 of Pat '926 to have the doping is by a solid phase diffusion process, as taught by claim 16 of Pat '926, for the purpose of providing 3D GAA capacitance devices to increase device density.
Claims 6-7 and 10-11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 and 7 of U.S. Patent No. 12,101,926 in view of Shimbo (US 2019/0164993).
Regarding claim 6, Pat '926 discloses the device of claim 1 as described above.
Pat '926 does not explicitly disclose the first nanostructure and the second nanostructure each have a cross-sectional profile that is rectangular.
Shimbo teaches, in at least figure 2 and related text, the device comprising the first nanostructure (11, [38]) and the second nanostructure (11, [38]) each have a cross-sectional profile that is rectangular ([83]), for the purpose of providing a semiconductor integrated circuit device including a nanowire FET ([7]) thereby improving density of integration.
Pat '926 and Shimbo are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '926 with the specified features of Shimbo because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '926 to have the first nanostructure and the second nanostructure each having a cross-sectional profile that is rectangular, as taught by Shimbo, for the purpose of providing a semiconductor integrated circuit device including a nanowire FET ([7], Shimbo) thereby improving density of integration.
Regarding claim 7, Pat '926 discloses the device of claim 1 as described above.
Pat '926 does not explicitly disclose the first nanostructure and the second nanostructure each have a cross-sectional profile that is elliptical.
Shimbo teaches, in at least figure 2 and related text, the device comprising the first nanostructure (11, [38]) and the second nanostructure (11, [38]) each have a cross-sectional profile that is elliptical ([83]), for the purpose of providing a semiconductor integrated circuit device including a nanowire FET ([7]) thereby improving density of integration.
Pat '926 and Shimbo are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '926 with the specified features of Shimbo because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '926 to have the first nanostructure and the second nanostructure each having a cross-sectional profile that is elliptical, as taught by Shimbo, for the purpose of providing a semiconductor integrated circuit device including a nanowire FET ([7], Shimbo) thereby improving density of integration.
Regarding claim 10, Pat '926 discloses the device of claim 9 as described above.
Pat '926 does not explicitly disclose a second source/drain in contact with the first and second nanostructures, opposite the first source/drain.
Shimbo teaches, in at least figure 2 and related text, the device comprising a second source/drain (P12, [38]) in contact with the first (11, [38]) and second (12, [38]) nanostructures, opposite the first source/drain (P11, [38]), for the purpose of providing a semiconductor integrated circuit device including a nanowire FET ([7]) thereby improving density of integration.
Pat '926 and Shimbo are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '926 with the specified features of Shimbo because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '926 to have the second source/drain in contact with the first and second nanostructures, opposite the first source/drain, as taught by Shimbo, for the purpose of providing a semiconductor integrated circuit device including a nanowire FET ([7], Shimbo) thereby improving density of integration.
Regarding claim 11, Pat '926 discloses the device of claim 1 as described above.
Pat '926 does not explicitly disclose the first nanostructure and the second nanostructure each have a nanosheet shape, a nanowire shape, or a nanotube shape.
Shimbo teaches, in at least figure 2 and related text, the device comprising the first nanostructure (11, [38]) and the second nanostructure (12, [38]) each have a nanosheet shape, a nanowire shape ([38]), or a nanotube shape, for the purpose of providing a semiconductor integrated circuit device including a nanowire FET ([7]) thereby improving density of integration.
Pat '926 and Shimbo are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '926 with the specified features of Shimbo because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '926 to have the first nanostructure and the second nanostructure each having a nanosheet shape, a nanowire shape, or a nanotube shape, as taught by Shimbo, for the purpose of providing a semiconductor integrated circuit device including a nanowire FET ([7], Shimbo) thereby improving density of integration.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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