Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,199,100 B2 to Liaw, hereinafter Liaw100.
Although the claims at issue are not identical, they are not patentably distinct from each other because the parent patent renders obvious the instant application.
Regarding independent claim 21: Liaw100 teaches (e.g., Claims 1-10) a device comprising:
a logic region having a first circuit region, a second circuit region, and a third circuit region,
wherein the second circuit region is disposed between the first circuit region and the third circuit region, the first circuit region abuts the second circuit region, and
the third circuit region does not abut and is spaced a distance from the second circuit region; wherein the first circuit region includes nanosheet transistors, the second circuit region includes nanowire transistors, and
the third circuit region includes fin-based transistors; and wherein the distance between the second circuit region and the third circuit region is at least four times a gate pith of gates of the nanowire transistors of the second circuit region (Claim 1).
Regarding claim 22: Liaw teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein: the first circuit region is configured for a first application; the second circuit region is configured for a second application; and the third circuit region is configured for a third application, wherein the first application, the second application, and the third application are different (Claim 4).
Regarding claim 23: Liaw100 teaches the claim limitation of the device of claim 22, on which this claim depends,
wherein: the nanosheet transistors are configured for high-speed operation; the nanowire transistors are configured for low power operation; and the fin-based transistors are configured for improving process margins (Claim 4).
Regarding claim 24: Liaw teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein a ratio of a channel width of the nanosheet transistors to a channel width of the nanowire transistors is about 1.3 to about 10 (Claim 8).
Regarding claim 25: Liaw100 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein a ratio of a gate length of the nanowire transistors to a gate length of the fin-based transistors is at least 1.5 (Claim 8).
Regarding claim 26: Liaw100 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein a ratio of a gate length of the nanosheet transistors to a gate length of the fin-based transistors is at least 1.5 (Claim 8).
Regarding claim 27: Liaw100 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein the fin-based transistors are first fin-based transistors, the device further comprising an input/output region having a fourth circuit region that includes second fin-based transistors, wherein the fourth circuit region does not abut the third circuit region of the logic region (Claim 2).
Regarding independent claim 21: Liaw100 teaches (e.g., Claims 11-18) a device comprising:
a logic region having a first circuit region, a second circuit region, and a third circuit region,
wherein the second circuit region is disposed between the first circuit region and the third circuit region, the first circuit region abuts the second circuit region, and
the third circuit region does not abut and is spaced a distance from the second circuit region; wherein the first circuit region includes nanosheet transistors, the second circuit region includes nanowire transistors, and
the third circuit region includes fin-based transistors; and wherein the distance between the second circuit region and the third circuit region is at least four times a gate pith of gates of the nanowire transistors of the second circuit region (Claim 1).
Regarding claim 28: Liaw100 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein the first circuit region and the second circuit region belong to a row that includes a plurality of circuit regions, wherein each of the first circuit region and the second circuit region provide a respective cell of the logic region (Claim 16).
Regarding claim 29: Liaw100 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein the first circuit region and the second circuit region belong to a column that includes a plurality of circuit regions, wherein each of the first circuit region and the second circuit region provide a respective cell of the logic region (Claim 18).
Regarding claim 30: Liaw100 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein the first circuit region is isolated from the second circuit region by a dummy gate structure (Claim 18).
Regarding independent claim 31: Liaw100 teaches (e.g. Claims 11-18) a device comprising: a logic region that includes a first area and a second area, wherein the second area is spaced a distance from and does not abut the first area;
wherein the first area includes first cells and second cells, the second area includes third cells, and the first cells, the second cells, and the third cells are different; wherein the first cells include nanosheet transistors, the second cells include nanowire transistors, and the third cells include fin-based transistors; wherein the first cells and the second cells are arranged in rows and columns to form a cell array, wherein at least one of the first cells abuts at least one of the second cell; and wherein the distance is between the first area and the second area is at least four times a gate pith of gates of the nanowire transistors of the second cells (Claim 14).
Regarding claim 32: Liaw100 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein the at least one of the first cells abuts the at least one of the second cell in a row of the cell array (Claim 14).
Regarding claim 33: Liaw100 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein the at least one of the first cells abuts the at least one of the second cell in a column of the cell array. (Claim 14)
Regarding claim 34: Liaw100 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein a ratio of a channel width of the nanosheet transistors to a channel width of the nanowire transistors is about 1.3 to about 10 (Claim 15).
Regarding claim 35: Liaw100 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein at least one of the first cells is configured as an NAND circuit and at least one of the second cells is configured as an inverter circuit (Claim 16).
Regarding claim 36: Liaw100 teaches the claim limitation of the device of claim 35, on which this claim depends,
wherein the NAND circuit abuts the inverter circuit (Claim 16).
Regarding claim 37: Liaw100 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein the distance between the first area and the second area is at least four times a channel pitch of the nanowire transistors of the second cells (Claim 17).
Regarding claim 38: Liaw100 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein the distance between the first area and the second area is at least four times a channel pitch of the nanosheet transistors of the first cells (Claim 17).
Regarding independent claim 39: Liaw339 teaches (e.g., Claims 19-20) a method comprising: forming nanosheet transistors in a first circuit region of a logic region; forming nanowire transistors in a second circuit region of the logic region, wherein the second circuit region abuts the first circuit region; and forming fin-based transistors in a third circuit region, wherein the second circuit region is disposed between the first circuit region and the third circuit region, the third circuit region does not abut and is spaced a distance from the second circuit region, and the distance between the second circuit region and the third circuit region is at least four times a gate pith of gates of the nanowire transistors of the second circuit region (Claim 19).
Regarding claim 40: Liaw100 teaches the claim limitation of the method of claim 39, on which this claim depends, wherein the forming the nanosheet transistors, the nanowire transistors, and the fin-based transistors includes: forming a semiconductor layer stack over the substrate in the first circuit region, the second circuit region, and the third circuit region; after removing the semiconductor layer stack from the third circuit region, forming a semiconductor layer over the substrate in the third device region; and processing the semiconductor layer stack in the first circuit region to form suspended nanosheets over the substrate, the semiconductor layer stack in the second circuit region to form suspended nanowires over the substrate, and the semiconductor layer in the third circuit region to form semiconductor fins extending from the substrate (Claim 20).
Claims 21-38 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 11,791,339 B2 to Liaw, hereinafter Liaw339.
Regarding independent claim 21: Liaw339 teaches (e.g., Claims 1-10) a device comprising:
a logic region having a first circuit region, a second circuit region, and a third circuit region,
wherein the second circuit region is disposed between the first circuit region and the third circuit region, the first circuit region abuts the second circuit region, and
the third circuit region does not abut and is spaced a distance from the second circuit region; wherein the first circuit region includes nanosheet transistors, the second circuit region includes nanowire transistors, and
the third circuit region includes fin-based transistors; and wherein the distance between the second circuit region and the third circuit region is at least four times a gate pith of gates of the nanowire transistors of the second circuit region (Claim 10).
Regarding claim 22: Liaw339 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein: the first circuit region is configured for a first application; the second circuit region is configured for a second application; and the third circuit region is configured for a third application, wherein the first application, the second application, and the third application are different (Claim 6).
Regarding claim 23: Liaw399 teaches the claim limitation of the device of claim 22, on which this claim depends,
wherein: the nanosheet transistors are configured for high-speed operation; the nanowire transistors are configured for low power operation; and the fin-based transistors are configured for improving process margins (Claim 7).
Regarding claim 24: Liaw339 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein a ratio of a channel width of the nanosheet transistors to a channel width of the nanowire transistors is about 1.3 to about 10 (Claim 8).
Regarding claim 25: Liaw339 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein a ratio of a gate length of the nanowire transistors to a gate length of the fin-based transistors is at least 1.5 (Claim 8).
Regarding claim 26: Liaw339 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein a ratio of a gate length of the nanosheet transistors to a gate length of the fin-based transistors is at least 1.5 (Claim 3).
Regarding claim 27: Liaw336 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein the fin-based transistors are first fin-based transistors, the device further comprising an input/output region having a fourth circuit region that includes second fin-based transistors, wherein the fourth circuit region does not abut the third circuit region of the logic region (Claim 1).
Regarding claim 28: Liaw339 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein the first circuit region and the second circuit region belong to a row that includes a plurality of circuit regions, wherein each of the first circuit region and the second circuit region provide a respective cell of the logic region (Claim 6).
Regarding claim 29: Liaw339 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein the first circuit region and the second circuit region belong to a column that includes a plurality of circuit regions, wherein each of the first circuit region and the second circuit region provide a respective cell of the logic region (Claim 7).
Regarding claim 30: Liaw339 teaches the claim limitation of the device of claim 21, on which this claim depends,
wherein the first circuit region is isolated from the second circuit region by a dummy gate structure (Claim 10).
Regarding independent claim 31: Liaw339 teaches (e.g., Claims 11-18) a
a device comprising: a logic region that includes a first area and a second area, wherein the second area is spaced a distance from and does not abut the first area;
wherein the first area includes first cells and second cells, the second area includes third cells, and the first cells, the second cells, and the third cells are different; wherein the first cells include nanosheet transistors, the second cells include nanowire transistors, and the third cells include fin-based transistors; wherein the first cells and the second cells are arranged in rows and columns to form a cell array, wherein at least one of the first cells abuts at least one of the second cell; and wherein the distance is between the first area and the second area is at least four times a gate pith of gates of the nanowire transistors of the second cells (Claim 14).
Regarding claim 32: Liaw339 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein the at least one of the first cells abuts the at least one of the second cell in a row of the cell array (Claim 14).
Regarding claim 33: Liaw339 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein the at least one of the first cells abuts the at least one of the second cell in a column of the cell array (Claim 15).
Regarding claim 34: Liaw339 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein a ratio of a channel width of the nanosheet transistors to a channel width of the nanowire transistors is about 1.3 to about 10 (Claim 12).
Regarding claim 35: Liaw339 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein at least one of the first cells is configured as an NAND circuit and at least one of the second cells is configured as an inverter circuit (Claim 16).
Regarding claim 36: Liaw339 teaches the claim limitation of the device of claim 35, on which this claim depends,
wherein the NAND circuit abuts the inverter circuit (Claim 16).
Regarding claim 37: Liaw339 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein the distance between the first area and the second area is at least four times a channel pitch of the nanowire transistors of the second cells (Claim 12).
Regarding claim 38: Liaw339 teaches the claim limitation of the device of claim 31, on which this claim depends,
wherein the distance between the first area and the second area is at least four times a channel pitch of the nanosheet transistors of the first cells (Claim 12).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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