DETAILED ACTION
This Office Action is in response to Application filed July 25, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Group I and Subspecies I drawn to the embodiment shown in Figs. 19 and 24A of current application in the reply filed on September 8, 2026 is acknowledged.
Claim Objections
Claims 26, 30 and 31 are objected to because of the following informalities:
On line 9 of claim 26, the limitation “additional interconnect dielectric material” should be amended, because (a) Applicants do not first claim “an interconnect dielectric material” or a step of depositing “an interconnect dielectric material”, either of which is required for Applicants to claim the step of “depositing additional interconnect level dielectric material (emphasis added)”, and (b) rather, Applicants claim “an interconnect level dielectric layer” on lines 2-3, which may or may not be associated with the unclaimed or unspecified “interconnect dielectric material”.
On lines 1 and 2 of claim 30 and on line 1 of claim 31, “a thickness” should be replaced with “the thickness”, because “a thickness” has already been recited on lines 15-16 of claim 26.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 26-35 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
(1) Regarding claim 26, Applicants did not originally disclose that “portions of the patterned second oxide semiconductor layer on either side of the trench comprise source/drain regions having a thickness greater than a thickness of the channel region” as recited on lines 14-16, because (a) Applicants claim that “portions of the patterned second oxide semiconductor layer on either side of the trench comprise source/drain regions”, which suggests that the newly claimed source/drain regions are smaller than or equal to the patterned second oxide semiconductor layer in terms of thickness, (b) however, Applicants did not originally disclose that the second oxide semiconductor layer 112 is thicker than the first oxide semiconductor layer 106 in Fig. 24A of current application, which is directed to Applicants’ elected species, assuming that the first oxide semiconductor layer 106 is associated with the claimed channel region, see the 35 USC 112(b) rejections below regarding the indefiniteness of the limitation “a channel region” recited in claim 26, (c) rather, Applicants originally disclosed that the combined thickness of the first and second oxide semiconductor layer is larger than the thickness of the first oxide semiconductor layer as shown in Fig. 11 of current application, (d) in addition, Applicants did not originally disclose that the drawings of current application are exactly to the scale, and therefore, even if the second oxide semiconductor layer 112 may look thicker than the first oxide semiconductor layer 106 in Fig. 24A of current application, the second oxide semiconductor layer 112 is not necessarily thicker than the first oxide semiconductor layer 106 in the claimed transistor, and (e) in Fig. 11 of current application, when there are both the first and second oxide semiconductor layer in the transistor just like Fig. 24A of current application, the thicknesses of the first and second oxide semiconductor layer look more or less the same, and therefore, Applicants did not originally disclose with any clarity the relative thickness of the first and second oxide semiconductor layer in Fig. 24A of current application.
(2) Further regarding claim 26, Applicants did not originally disclose for the elected species shown in Fig. 24A of current application that “portions of the patterned second oxide semiconductor layer on either side of the trench comprise source/drain regions having a thickness greater than a thickness of the channel region” recited on lines 14-16, because (a) as discussed below under the 35 USC 112(b) rejections, unlike the nonelected species shown in Fig. 12A of current application, there is no well-defined “channel region” and “source/drain regions” in the transistor shown in Fig. 24A of current application since an electrical current would flow as illustrated below between the top rectangular surface portions of the patterned second oxide semiconductor layer 112 that function as “source/drain regions” and the top central portion of the patterned first oxide semiconductor layer 106 that functions as an actual channel region, (b) in other words, the thickness of the claimed “source/drain regions” would not be the same with the thickness of the patterned second oxide semiconductor layer since an electrical current would not flow in a vertical direction between the contacts 114 and the second oxide semiconductor layer 112 in the elected species shown in Fig. 24A of current application, and (c) furthermore, the thickness of “the channel region” would not be the same with the thickness of the patterned first oxide semiconductor layer 106 either since an electrical current would not flow in a vertical direction between the contacts 114 and the second oxide semiconductor layer 112 in the elected species shown in Fig. 24A of current application.
PNG
media_image1.png
526
584
media_image1.png
Greyscale
Claims 27-35 depend on claim 26, and therefore, claims 27-35 also fail to comply with the written description requirement.
(3) Regarding claim 30, Applicants did not originally disclose the claimed ratio of the thickness of the source/drain regions to the thickness of the channel region, because (a) this limitation appears to be directed to the nonelected species shown in Fig. 12A of current application, (b) as discussed above, the elected species shown in Fig. 24A of current application is very distinct from the nonelected species shown in Fig. 12A of current application, and therefore, there is no clear disclosure that the claimed ratio measured from the nonelected species shown in Fig. 12A of current application is also measured from the elected species shown in Fig. 24A of current application, and (c) furthermore, as discussed above, the channel region and the source/drain region in the elected species shown in Fig. 24A of current application are variable in their sizes depending on the operating conditions of the claimed transistor, and therefore, the claimed ratio of the thickness of the source/drain regions to the thickness of the channel region was not originally disclosed by Applicants for the species shown in Fig. 24A of current application.
(4) Regarding claims 31 and 32, Applicants did not originally disclose the claimed thickness of the channel region and the claimed combined thickness of the patterned first and second oxide semiconductor layer recited in claim 31, and the length of the channel region recited in claim 32 for the same reasons stated above with regard to noncompliance with a written description requirement of claim 30.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-9, 12, 14 and 21-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 7, it is not clear what the step of “forming a channel region in the first oxide semiconductor layer” recited on line 4 suggests, because (a) Applicants claim as if the step of “depositing a first oxide semiconductor layer” recited on line 2 and the step of “forming a channel region in the first oxide semiconductor layer” recited on line 4 were separate steps, (b) however, it does not appear that Applicants performed any additional step other than “depositing a first oxide semiconductor layer” in forming “a channel region in the first oxide semiconductor layer”, (c) in other words, it appears that Applicants originally disclosed that the channel region is automatically and/or spontaneously formed as soon as the first oxide semiconductor layer is formed, i.e. the channel region is a part of the first oxide semiconductor layer without any distinction from the remainder of the first oxide semiconductor layer, and (d) therefore, the two steps recited on lines 2 and 4 cited above appear to be contradictory to Applicants’ original disclosure of a single step of forming both the first oxide semiconductor layer and the channel region, and therefore, claim 7 may also fail to comply with the written description requirement since current Application is a Divisional Application of the parent applications 17/215,997 and 18/366,725.
(2) Also regarding claim 7, it is not clear what the “source/drain regions” recited on line 5 refer to, because (a) unlike the embodiment shown in Fig. 12A, which is an embodiment Applicants elected for prosecution of the parent applications 17/215,997 and 18/366,725, and whose source/drain regions are the rectangular regions illustrated below since the leftmost region of the first oxide semiconductor layer 106 and the second oxide semiconductor layer 112 on the left side, and the rightmost region of the first oxide semiconductor layer 106 and the second oxide semiconductor layer 112 on the right side would function as source/drain regions as they are electrically connected and directly in contact with the contacts 114 that are laterally coextensive with the second oxide semiconductor layer 112,
PNG
media_image2.png
536
584
media_image2.png
Greyscale
Applicants’ elected species shown in Fig. 24A of current application does not comprise the coextensive second oxide semiconductor layer and the contacts 114 shown in Fig. 12A of current application, (b) therefore, if the rectangular areas shown in Fig. 12A of current application illustrated above are source/drain regions of the embodiment shown in Fig. 12A of current application, source/drain regions of the embodiment shown in Fig. 24A of current application would be top surface regions illustrated below since an electrical current would not flow in a vertical direction between the second oxide semiconductor layer 112 and the first oxide semiconductor layer 106, which is the case with the embodiment shown in Fig. 12A of current application, (c) rather, an electrical current for the transistor shown in Fig. 24A of current application is likely to flow as illustrated below,
PNG
media_image1.png
526
584
media_image1.png
Greyscale
(d) in this case, the entirety of the second oxide layer 112 on the left side and on the right side would not be able to function as source/drain regions since an electrical current would not flow in a vertical direction between the contacts 114 and the first oxide semiconductor layer 106, and (e) therefore, without Applicants’ specifically claiming what the “source/drain regions” refer to in the elected species shown in Fig. 24A of current application, the limitation “a thickness of the source/drain regions is greater than a thickness of the channel region” recited on lines 5-7 may not be unambiguously determined, and if the source/drain regions are surface regions of the second oxide semiconductor layer 112 in Fig. 24A of current application, then the thickness of the source/drain regions may be smaller than the thickness of the channel region in Fig. 24A of current application contradictory to what Applicants claim in claim 7.
(3) Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: how and where the “source/drain regions” recited on line 5 are formed, because (a) as currently claimed, it appears that Applicants claim that the “source/drain regions” are formed inside the first oxide semiconductor layer on either side of the channel region, which does not appear to be Applicants’ originally disclosed invention, (b) also, as discussed above, it is not clear what the claimed “source/drain regions” refer to in the first place, and (c) therefore, it is not clear how and where the “source/drain regions” are formed.
(4) Further regarding claim 7, it is not clear what the limitation “a thickness of the source/drain regions is greater than a thickness of the channel region” recited on lines 5-7 suggests, because (a) Applicants did not originally disclose and do not specifically claim which part of the first oxide semiconductor layer is “a channel region” on line 4 in the embodiment shown in Fig. 24A of current application, (b) a channel region is different from a channel layer, and therefore, “a thickness of the channel region” in Fig. 24A of current application would depend on the operating conditions of the transistor, which Applicants do not specifically claim, (c) furthermore, as discussed above, “the source/drain region” in the elected species shown in Fig. 24A of current application are top surface regions directly adjacent to the contacts 114, whose thickness also depends on the operating conditions of the transistor, which Applicants do not specifically claim, either, and (d) therefore, with the thicknesses of the channel region and the source/drain regions varying with the operating conditions of the transistor, the limitation cited above cannot be unambiguously determined by one of ordinary skill in the art.
(5) Regarding claims 7 and 8, it is not clear what the “source/drain regions” recited on line 5 of claim 7 suggest, because (a) Applicants further claim in claim 8 a step of “depositing a second oxide semiconductor layer in the source/drain regions”, which basically suggests that the source/drain regions recited on line 5 of claim 7 are empty spaces, and (b) in this case, it is not clear how one can measure a thickness of “the source/drain regions” or empty spaces to compare the thickness of the empty spaces with the thickness of the unspecified channel region as recited on lines 5-7 of claim 7.
Claims 8, 9, 12, 14 and 21-25 depend on claim 7, and claims 9 and 21 depend on claim 8, and therefore, claims 8, 9, 12, 14 and 21-25 are also indefinite.
(6) Regarding claim 22, it is not clear what the limitations of claim 22 suggest, because (a) the steps recited in the new claim 22 are not compatible with the limitations of claim 7 since claim 7 recites a step of “forming a channel region in the first oxide semiconductor layer (emphasis added)” on line 4 of claim 7, (b) however, the steps recited in the new claim 22 reciting etching of the additional interconnect level dielectric material and the second oxide semiconductor layer has nothing to do with the step of “forming a channel region in the first oxide semiconductor layer (emphasis added)” since the material composition and electrical characteristics of the first oxide semiconductor layer do not change by the steps of etching of the additional interconnect level dielectric material and the second oxide semiconductor layer, (c) furthermore, Applicants claim the step of “forming source/drain regions on either side of the channel region” on line 5 of claim 7, and therefore, in view of the claim limitations of the new claim 22, when the source/drain regions are formed, there was no channel region contradictory to the limitation of “forming source/drain regions on either side of the channel region” on line 5 of claim 7, and (d) finally, it appears that Applicants claim that “the channel region” is formed or disposed “over a central portion of the first oxide semiconductor layer” as recited on line 3 of claim 22, which is contradictory to the channel region in the first oxide semiconductor layer recited in claim 7. Claims 23-25 depend on claim 22, and therefore, claims 23-25 are also indefinite.
(7) Regarding claim 26, it is not clear what “a channel region” recited on line 13 refers to, because (a) as Applicants claim on line 4 of claim 7, “a channel region” should be a part of the first oxide semiconductor layer recited on line 2 of claim 26, (b) however, Applicants claim that the additional interconnect level dielectric material and the patterned second oxide semiconductor layer are etched “in a channel region” on lines 12-13 when the additional interconnect level dielectric material and the patterned second oxide semiconductor layer do not appear to have anything to do with “a channel region” located in the first oxide semiconductor layer, and (c) therefore, it is not clear whether Applicants claim that a portion of the patterned second oxide semiconductor layer remains in the claimed transistor to function as “a channel region”, which appears to be a strict interpretation of the limitation recited on lines 12-13, or whether Applicants claim that the additional interconnect level dielectric material and the patterned second oxide semiconductor layer are etched above a central region of the patterned first oxide semiconductor layer that will eventually function as “a channel region” when the claimed transistor is completed.
(8) Also regarding claim 26, it is not clear how “the patterned second oxide semiconductor layer” is etched “in a channel region” as recited on lines 12-13, which appears to suggest that at least a portion of the patterned second oxide semiconductor layer is “in a channel region”, and then “portions of the patterned second oxide semiconductor layer on either side of the trench comprise source/drain regions having a thickness greater than a thickness of the channel region” as recited on lines 14-16, because (a) these two limitations recited on lines 12-13 and on lines 14-16 are contradictory to each other since (i) when an entire vertical portion of the patterned second oxide semiconductor layer is “in a channel region”, “portions of the patterned second oxide semiconductor layer on either side of the trench” comprising “source/drain regions” should have “a thickness” the same with “a thickness of the channel region”, and (ii) when a portion of an entire vertical portion of the patterned second oxide semiconductor layer is “in a channel region”, “portions of the patterned second oxide semiconductor layer on either side of the trench” comprising “source/drain regions” may have “a thickness greater than a thickness of the channel region” or “a thickness” smaller “than a thickness of the channel region”, depending on the depth of the trench, (b) if “a channel region” recited on line 13 is an arbitrary region that comprises a central portion of the patterned first oxide semiconductor layer and a central portion of the patterned second oxide semiconductor layer, then the limitation “portions of the patterned second oxide semiconductor layer on either side of the trench comprise source/drain regions having a thickness greater than a thickness of the channel region” recited on lines 14-16 cannot be unambiguously determined since “a channel region” recited on line 13 is an arbitrary region.
(9) Further regarding claim 26, it is not clear what “a channel region” recited on line 13 and “source/drain regions” recited on line 15 refer to, because (a) as discussed above with regard to claim 7, for the elected species shown in Fig. 24A of current application, a size of “a channel region” and a size of “source/drain regions” would vary depending on the operating conditions unlike the nonelected species shown in Fig. 12A of current application, and (b) therefore, the limitation “portions of the patterned second oxide semiconductor layer on either side of the trench comprise source/drain regions having a thickness greater than a thickness of the channel region” recited on lines 14-16 cannot be unambiguously determined since the thickness of “a channel region” recited on line 13 and the thickness of “source/drain regions” recited on line 15 depend on operating conditions of the claimed transistor.
Claims 27-35 depend on claim 26, and therefore, claims 27-35 also fail to comply with the written description requirement.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9, 12, 14 and 21, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Asami (US 2018/0019343)
Regarding claim 7, Asami discloses a method of making a transistor (transistor in circled area of Fig. 29A illustrated below) comprising: an interconnect level dielectric layer (unmarked area between bottom gate electrode and oxide semiconductor layer).
PNG
media_image3.png
240
486
media_image3.png
Greyscale
Asami differs from the claimed invention by not comprising: depositing a first oxide semiconductor layer over the interconnect level dielectric layer; forming a channel region in the first oxide semiconductor layer; and forming source/drain regions on either side of the channel region, wherein a thickness of the source/drain regions is greater than a thickness of the channel region.
Asami further discloses a method of making a transistor (transistor formed from intermediate transistor structure shown in Fig. 1) comprising: depositing a first oxide semiconductor layer (121) ([0134]) over a dielectric layer (110) ([0132]), which correspond to an interconnect level dielectric layer shown in Fig. 29A of Asami; forming a channel region (central portion of 121) in the first oxide semiconductor layer, which is indefinite as discussed above under the 35 USC 112(b) rejections; and forming source/drain regions (composite regions of left/right region of 121, left/right region of 122 and 130/140) ([0106]) on either side of the channel region, wherein a thickness of the source/drain regions is greater than a thickness of the channel region, because while the channel region corresponds to a central portion of the oxide semiconductor layer 121, the source/drain regions corresponds to composite regions of the left/right region of the oxide semiconductor layer 121, the left/right region of oxide semiconductor layer 122 and the source electrode 130/drain electrode140.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method of making the transistor shown in Fig. 29A of Asami can comprise depositing a first oxide semiconductor layer over the interconnect level dielectric layer, and forming source/drain regions on either side of the channel region of the intermediate transistor structure similar to that shown in Fig. 1 of Asami, because (a) the intermediate transistor structure shown in Fig. 1 of Asami is substantially identical to the transistor included in the circular area of Fig. 29A of Asami illustrated above except for the unlabeled bottom gate electrode shown in Fig. 29A of Asami, and (b) therefore, the intermediate transistor structure shown in Fig. 1 of Asami can be slightly modified by incorporating the unlabeled bottom gate electrode and underlying transistor structure shown in Fig. 29A of Asami to manufacture the multilevel transistor shown in Fig. 29A of Asami.
Regarding claims 8 and 9, Asami further comprises depositing a second oxide semiconductor layer (122) in the source/drain regions (composite regions of left/right region of 121, left/right region of 122 and 130/140), which is also indefinite as discussed above under 35 USC 112(b) rejections, wherein a material of the second oxide semiconductor layer is different than that of the first oxide semiconductor layer ([0157]) (claim 8), wherein the second oxide semiconductor layer (122) is deposited over the first oxide semiconductor layer (121), wherein the source/drain regions (composite regions of left/right region of 121, left/right region of 122 and 130/140) comprise the first oxide semiconductor layer and the second oxide semiconductor layer (claim 9).
Regarding claim 12, Asami further comprises for the method of claim 7 depositing a metal gate layer (160) ([0203]); and depositing a dielectric layer (150) ([0196]), wherein the first oxide semiconductor layer (121) comprises one of InxGayZnzOw, In2O, Ga2O3, ZnO, or InxSnyOz (“an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd)” in [0141]).
Asami differs from the claimed invention by not showing that the dielectric layer comprises one of SiO2, Al2O3, HfO2, HZO, HfSiOx, HfLaOx, or multilayers thereof.
Asami further discloses that the dielectric layer 150 comprises silicon oxide (SiOx), aluminum oxide (AlOx) or hafnium oxide (HfOx) ([0196]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the dielectric layer disclosed by Asami can comprise one of the claimed material compositions recited in claim 12, because (a) SiO2, Al2O3 and HfO2 are stoichiometric compositions of silicon oxide, aluminum oxide and hafnium oxide disclosed by Asami, and have been commonly employed as insulating material compositions due to their well-known insulating characteristics and dielectric constants, and (b) it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use, In re Leshin, 125 USPQ 416.
Regarding claims 14 and 21, Asami further discloses that the metal gate layer (160) is deposited over the first oxide semiconductor layer (121) and the dielectric layer (150) (claim 14), further comprising depositing additional interconnect level dielectric material (dielectric layer in Fig. 29A corresponding to 175 in Fig. 1) ([0155]) over the first oxide semiconductor layer (121) and the second oxide semiconductor layer (122) such that the first oxide semiconductor layer and the second oxide semiconductor layer are embedded in the additional interconnect level dielectric material (claim 21).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Matsuda et al. (US 9,954,003)
Sharma et al. (US 2021/0408291)
Onuki et al. (US 2022/0328486)
Onuki et al. (US 2020/0144310)
Ishizu et al. (US 2018/0075900)
Yamazaki et al. (US 12,453,187)
Shimomura et al. (US 9,954,113)
Yamazaki et al. (US 12,136,663)
Sasagawa et al. (US 10,181,531)
Yamazaki et al. (US 9,450,080)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 AM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 September 17, 2026
Prosecution Insights