DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/25/2024, 10/17/2024, 6/27/2025 and 2/25/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 14 objected to because of the following informalities: the claim appears to have a typographical error, "The semiconductor device of claim 9, wherein the opening is further in the etch stop layer.". For the purpose of examination, the examiner will interpret the above limitation as " The semiconductor device of claim [[9]]13, wherein the opening is further in the etch stop layer." or “The semiconductor device of claim 9, wherein the opening is further in an etch stop layer.”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bark et al. US 2018/0261546.
Re claim 17, Bark teaches a semiconductor device (fig11J and 17B), comprising:
a fin structure (FA, fig17B, [135]) in a substrate (110, fig17B, [26]);
a first dielectric layer (662 as SiCON, fig17B, [133]) over the substrate;
a source/drain contact (part of 632 as Ti in contact with 672, fig17B, [138]) in the first dielectric layer and over the fin structure;
a second dielectric layer (680 as SiN, fig17B, [134]) over the first dielectric layer (662 as SiCON, fig17B, [133]); and
an interconnect structure (634, fig17B, [138]) in the second dielectric layer (680 as SiN, fig17B, [134]) and over the source/drain contact (part of 632 as Ti in contact with 672, fig17B, [138]).
Re claim 18, Bark teaches the semiconductor device of claim 17, wherein a portion of the second dielectric layer (680 as SiN, fig17B, [134]), intersecting with sidewalls of the interconnect structure (634, fig17B, [138]), comprises a barrier layer (632 contacting 680, fig17B, [138]).
Re claim 19, Bark teaches the semiconductor device of claim 17, wherein a top width of the interconnect structure (width of top part of 634 in layer 680, fig17B) is greater than a bottom width of the interconnect structure (width of bottom part of 134 in layer 662, fig17B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bark et al. US 2018/0261546 in view of Kuratomi et al. US 2020/0144073.
Re claim 1, Bark teaches a semiconductor device (fig11J), comprising:
one or more dielectric layers (124-122 or 154-156, fig11J, [30, 34, 35]);
an interconnect structure (136 or 166, fig11J, [27, 35]) included in the one or more dielectric layers (124-122 or 154-156, fig11J, [30, 34, 35]); and
a first barrier layer (part of 132 as Ti in contact with 124-122 or part of 162 as Ti in contact with 154-156, fig11B, [31, 35]) between the interconnect structure (136 or 166, fig11J, [27, 35]) and at least one of the one or more dielectric layers (124-122 or 154-156, fig11J, [30, 34, 35]),
Bark does not explicitly show wherein the first barrier layer includes a compound containing titanium, silicon, and oxide.
Kuratomi teaches Ti formed on SiO2 layer transform to TiSiOx and Ti Formed on SiN layer transform to TiSiN ([22]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bark and Kuratomi to form the barrier with the steps of Kuratomi to reduce oxidation between layers and reduce contact resistance (Kuratomi, [21, 25]).
Bark in view of Kuratomi teaches wherein the first barrier layer includes a compound containing titanium, silicon, and oxide (Ti 132 in contact with 124 turn to TiSiOx or Ti 162 in contact with 156 turn to TiSiOx, fig11J, [33, 34, 35]).
Re claim 2, Bark modified above teaches the semiconductor device of claim 1, further comprising: a metal layer (120, fig11J, [33]) under the interconnect structure (136, fig11J, [27]), wherein the metal layer includes a contact that is electrically connected to a source/drain region of the semiconductor device (120 connected to S/D of transistor on 110, fig11J, [33]); and a titanium (Ti) layer (Ti 132 in contact with W 120 stay as Ti, fig11B, [31,33]) on the metal layer, wherein the interconnect structure (136, fig11J, [27]) is included on the titanium layer.
Re claim 3, Bark modified above teaches the semiconductor device of claim 2, wherein the titanium layer (Ti 132 in contact with W 120 stay as Ti, fig11B, [31,33]) is adjacent to a silicon nitride layer (122 as SiN, fig11J, [33, 34]) of the one or more dielectric layers; and wherein the titanium layer is below a silicon oxide layer (124 as silicon oxide, fig11J, [33, 34]) of the one or more dielectric layers.
Re claim 4, Bark modified above teaches the semiconductor device of claim 1, further comprising a metal source/drain contact (222) (120, fig11J, [33]), wherein the interconnect structure is included directly on the metal source/drain contact (136 with Ti in contact with W 120, fig11J, [31, 33]).
Re claim 5, Bark modified above teaches the semiconductor device of claim 1, wherein the interconnect structure comprises ruthenium (136 as Ru, fig11J, [28]).
Re claim 6, Bark modified above teaches the semiconductor device of claim 1, wherein the one or more dielectric layers comprise: a silicon nitride (SixNy) layer (122 as SiN, fig11J, [33, 34]); a silicon oxide (SiOx) layer (124 as silicon oxide, fig11J, [33, 34]); and wherein the first barrier layer is included between the interconnect structure (136, fig11J, [27]) and the silicon oxide layer (Ti 132 in contact with 124 turn to TiSiOx, fig11B, [33, 34]); and wherein the semiconductor device further comprises: a second barrier layer (Ti 132 in contact with 122 turn to TiSiN), between the interconnect structure (136, fig11J, [27]) and the silicon nitride layer (122 as SiN, fig11J, [33, 34]), comprising a compound containing titanium, silicon, and nitride (Ti 132 in contact with 122 turn to TiSiN).
Re claim 7, Bark modified above teaches the semiconductor device of claim 6, wherein the silicon oxide layer (124 as silicon oxide, fig11J, [33, 34]) is above the silicon nitride layer (122 as SiN, fig11J, [33, 34]); and wherein the first barrier layer (Ti 132 in contact with 124 turn to TiSiOx, fig11B, [33, 34]) is above the second barrier layer (Ti 132 in contact with 122 turn to TiSiN, fig11J).
Re claim 8, Bark modified above teaches the semiconductor device of claim 1, further comprising: a metal gate structure (gate of transistor in 110 GL, fig11J and 17C, [33, 133]]); and a metal gate contact (CP2, fig17C, [137]) over the metal gate structure, wherein the one or more dielectric layers (694 as silicon oxide and etch stop layer in fig17C as 156/154 in fig11J) are included above the metal gate contact (CP2, fig17C, [137]), and wherein the interconnect structure (698 as Ru with barrier Ti, fig17C, [140]) is included over the metal gate contact (CP2, fig17C, [137]).
Re claim 9, Bark modified above teaches a semiconductor device (fig11J), comprising:
one or more dielectric layers (124-122 or 154-156, fig11J, [30, 34, 35]) having an opening (H1 or H2, fig11A and 11I, [64, 80]) over a source/drain contact (120, fig11J, [33]);
a barrier layer (part of 132 as Ti in contact with 124-122 or part of 162 as Ti in contact with 154-156, fig11B, [31, 35]); and
a ruthenium-containing (Ru) interconnect structure (136 or 166, fig11J, [27, 35]) over the source/drain contact, over the barrier layer, and in the opening.
Bark does not explicitly show a barrier layer in sidewalls of the opening.
Kuratomi teaches Ti formed on SiO2 layer transform to TiSiOx and Ti Formed on SiN layer transform to TiSiN ([22]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bark and Kuratomi to form the barrier with the steps of Kuratomi to reduce oxidation between layers and reduce contact resistance (Kuratomi, [21, 25]).
Re claim 10, Bark modified above teaches the semiconductor device of claim 9, wherein the barrier layer includes a compound containing titanium, silicon, and oxide (Ti 132 in contact with 124 turn to TiSiOx, fig11J, [33, 34]).
Re claim 11, Bark modified above teaches the semiconductor device of claim 9, further comprising: a metal layer (136, fig11J, [27, 35]) over the source/drain contact (120, fig11J, [33]), wherein the Ru interconnect structure (166, fig11J, [35])) is separated from the source/drain contact (120, fig11J, [33]) by the metal layer (136, fig11J, [27, 35]).
Re claim 12, Bark modified above teaches the semiconductor device of claim 9, wherein the Ru interconnect structure (136 with Ti in contact with W 120, fig11J, [31, 33]]) is formed directly on the source/drain contact (120, fig11J, [33]).
Re claim 13, Bark modified above teaches the semiconductor device of claim 9, further comprising: an etch stop layer (122, fig11J, [34]) over the source/drain contact (120, fig11J, [33]) and under the one or more dielectric layers (124 fig11J, [34]).
Re claim 14, Bark modified above teaches the semiconductor device of claim [[9]]13, wherein the opening (H1, fig11A, [64]) is further in the etch stop layer (122, fig11J, [34]).
Re claim 15, Bark modified above teaches the semiconductor device of claim 14, wherein a width of the opening (width of VH1, fig11A, [64]) in the etch stop layer (122, fig11J, [34]) is less than a width of the opening in the one or more dielectric layers (width of LH1, fig11A, [64]).
Re claim 16, Bark modified above teaches the semiconductor device of claim 14, wherein the barrier layer (Ti 132 in contact with 122 turn to TiSiN and Ti in contact with 124 turn to TiSiOx, fig11B, [33, 34]) is further in the etch stop layer (122, fig11J, [34]).
Re claim 13, Bark modified above teaches the semiconductor device of claim 9, further comprising: an etch stop layer (154, fig11J, [35]) over the source/drain contact (120, fig11J, [33]) and under the one or more dielectric layers (156, fig11J, [35]).
Re claim 14, Bark modified above teaches the semiconductor device of claim [[9]]13, wherein the opening (H2, fig11I, [80]) is further in the etch stop layer (154, fig11J, [35]).
Re claim 20, Bark modified above teaches the semiconductor device of claim 14, wherein a bottom width of interconnect structure (bottom width of 166, fig11J, [35]) is less than a top width of the source/drain contact (top width 120, fig11J, [33]).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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