DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 2 and 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the forming the first undoped epitaxial layer and the second undoped epitaxial layer and the forming the first doped epitaxial layer and the second doped epitaxial layer are performed ex-situ,” as recited in claim 2.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “simultaneously forming the first undoped semiconductor layer in the first source/drain recess and the second undoped semiconductor layer in the second source/drain recess;
simultaneously forming the first doped semiconductor layer in the first source/drain recess and the second undoped semiconductor layer in the second source/drain recess; and
breaking vacuum between the forming of the first undoped semiconductor layer and the second undoped semiconductor layer and the forming of the first doped semiconductor layer and the second doped semiconductor layer,” as recited in claim 10.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “simultaneously forming the first undoped semiconductor layer in the first source/drain recess and the second undoped semiconductor layer in the second source/drain recess;
masking the second device region while forming the first doped semiconductor layer; masking the first device region while forming the second doped semiconductor layer; and
breaking vacuum between the forming of the first undoped semiconductor layer and the second undoped semiconductor layer and the forming of the first doped semiconductor layer and the second doped semiconductor layer,” as recited in claim 11.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claims 19 and 20 recites the limitation "threshold width” The meaning of the claim term is indefinite because the claim term is not used or defined in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 19 and 20 recites the limitation “threshold width.” There is insufficient antecedent basis for this limitation in the claim because the meaning of the term “threshold width” is unclear.
For purpose of compact prosecution, the meaning of the term “threshold width” is defined as source/drain recess width.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17-18 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Jang et al. (U.S. 2020/0220018 A1, hereinafter refer to Jang).
Regarding Claim 17: Jang discloses a method (see Jang, Figs.6 and 11K as shown below and ¶ [0002]) comprising:
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receiving a device precursor having an active region disposed over a substrate (101), wherein the active region includes a semiconductor layer stack (120/140) disposed over a substrate extension (see Jang, Fig.11C);
forming source/drain recesses (RC) in first portions of the active region by removing the semiconductor layer stack (120/140) and a portion of the substrate extension, wherein the source/drain recess (RC) extends a first depth into the substrate extension and a second portion of the active region is disposed between the source/drain recesses (RC), wherein the second portion of the active region includes a remainder of the semiconductor layer stack (120/140) disposed over the substrate extension (see Jang, Figs.11D-11F);
forming undoped epitaxial layers (151 at the bottom surface of recess region RC) in bottom portions of the source/drain recesses (RC) that are formed by the substrate extension, wherein the undoped epitaxial layers (151 at the bottom surface of recess region RC) have a height that is less than the first depth and the source/drain recesses (RC) extend a second depth into the substrate extension after forming the undoped epitaxial layers, wherein the second depth is less than the first depth, and further wherein the forming of the source/drain recesses (RC) and the forming of the undoped epitaxial layers (151 at the bottom surface of recess region RC) are tuned to provide the first depth and the thickness, respectively, based on a size of the active region (see Jang, Fig.11G); and
forming doped epitaxial layers (152/154) over the undoped epitaxial layers (151 at the bottom surface of recess region RC), wherein the doped epitaxial layers (152/154) fill remainders of the source/drain recesses (RC) (see Jang, Figs.11H-11I).
Regarding Claim 18: Jang discloses a method as set forth in claim 17 as above. Jang further teaches wherein the semiconductor layer stack (120/140) includes first semiconductor layers (140) and second semiconductor layers (120), the method further comprising: replacing end portions of the second semiconductor layers (120) with inner spacers (130) before forming the undoped epitaxial layers (151) (see Jang, Figs.11F-11G); and
replacing central portions of the second semiconductor layers (120) with a gate stack (162/165) after forming the doped epitaxial layers (152/154) (see Jang, Figs.11I-11J and Fig.11K as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 5, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (U.S. 2021/0066452 A1, hereinafter refer to Liaw) in view of Jang et al. (U.S. 2020/0220018 A1, hereinafter refer to Jang).
Regarding Claim 1: Liaw discloses a method (see Liaw, Figs.5-7 and 11 as shown below and ¶ [0110]) comprising:
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forming a first source/drain recess (133) that extends through first semiconductor layers (261) to a first depth (D1) into a semiconductor substrate (101) and a second source/drain recess (133) that extends through second semiconductor layers (261) to a second depth (D2) into the semiconductor substrate (101), wherein the first depth (D1) is different than the second depth (D2), the first source/drain recess (133) is in a first active region of a first size, the second source/drain recess (133) is in a second active region of a second size, and the second size is different than the first size (see Liaw, Fig.5 as shown above, ¶ [0045], ¶ [0049], and ¶ [0058]).
Liaw is silent upon explicitly disclosing wherein forming a first undoped epitaxial layer in the first source/drain recess and a second undoped epitaxial layer in the second source/drain recess, wherein a first thickness of the first undoped epitaxial layer is less than the first depth and a second thickness of the second undoped epitaxial layer is less than the second depth; and
forming a first doped epitaxial layer in the first source/drain recess and over the first undoped epitaxial layer and a second doped epitaxial layer in the second source/drain recess and over the second undoped epitaxial layer.
For support see Jang, which teaches forming a first undoped epitaxial layer (151 at the bottom surface of recess region RC) in the first source/drain recess and a second undoped epitaxial layer (151 at the bottom surface of recess region RC) in the second source/drain recess, wherein a first thickness of the first undoped epitaxial layer (151 at the bottom surface of recess region RC) is less than the first depth and a second thickness of the second undoped epitaxial layer (151 at the bottom surface of recess region RC) is less than the second depth (see Jang, Figs.6 and 11K as shown below, ¶ [0058], and ¶ [0113]- ¶ [0114]); and
forming a first doped epitaxial layer (152/154) in the first source/drain recess and over the first undoped epitaxial layer (151 at the bottom surface of recess region RC) and a second doped epitaxial layer (152/154) in the second source/drain recess and over the second undoped epitaxial layer (151 at the bottom surface of recess region RC) (see Jang, Figs.6 and 11K as shown above, and ¶ [0113]- ¶ [0114]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Liaw and Jang to enable forming a first doped epitaxial layer in the first source/drain recess and over the first undoped epitaxial layer and a second doped epitaxial layer in the second source/drain recess and over the second undoped epitaxial layer as taught by Jang in order to improve the electrical properties of semiconductor device.
Regarding Claim 5: Liaw as modified teaches a method as set forth in claim 1 as above. The combination of Liaw and Jang further teaches wherein: the first depth (D1= between about 2 nm and about 30 nm) is greater than (less than or equal to) a first distance (Th1 + Th2 = between about 8 and about 30) between a topmost surface of the first semiconductor layers and a topmost surface of the semiconductor substrate (see Liaw, Figs.5-6 as shown above, ¶ [0021], and ¶ [0044]); and
the second depth (D1= between about 2 nm and about 30 nm) is less than a second distance (Th1 + Th2 = between about 8 and about 30) between a topmost surface of the second semiconductor layers and the topmost surface of the semiconductor substrate (see Liaw, Figs.5-6 as shown above, ¶ [0021], and ¶ [0044]).
The combination of Liaw and Jang teaches an overlapping ranges as shown above; hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the first depth relative to the first distance and the second depth relative to the second distance through routine experimentation and optimization to obtain optimal or desired device performance because the first depth relative to the first distance and the second depth relative to the second distance is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 7: Liaw as modified teaches a method as set forth in claim 1 as above. The combination of Liaw and Jang is silent upon explicitly disclosing wherein the first undoped epitaxial layer and the second undoped epitaxial layer have different cross-sectional profiles.
However, the combination of Liaw and Jang teaches wherein the first undoped epitaxial layer and the second undoped epitaxial layer have the same cross-sectional profiles (see Jang, Figs.6 and 11K as shown above).
Hence, the configuration of the claimed the first undoped epitaxial layer and the second undoped epitaxial layer was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed the first undoped epitaxial layer and the second undoped epitaxial layer was significant.
Claim(s) 8-9 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (U.S. 2021/0066452 A1, hereinafter refer to Liaw) in view of Jang et al. (U.S. 2020/0220018 A1, hereinafter refer to Jang) and Lin et al. (U.S. 2021/0098311 A1, hereinafter refer to Lin).
Regarding Claim 8: Liaw discloses a method (see Liaw, Figs.5-7 and 11 as shown above and ¶ [0110]) comprising:
forming a first source/drain recess (133) in a first device region (106), wherein the first source/drain recess has a first bottom portion formed by a first semiconductor extension, wherein the first source/drain recess (133) extends a first depth (D1) into the first semiconductor extension (see Liaw, Fig.5 as shown above, ¶ [0045], ¶ [0049], and ¶ [0058]);
forming a second source/drain recess (133) in a second device region (108), wherein the second source/drain recess (133) has a second bottom portion formed by a second semiconductor extension, wherein the second source/drain recess (133) extends a second depth (D2) into the second semiconductor extension (see Liaw, Fig.5 as shown above, ¶ [0045], ¶ [0049], and ¶ [0058]).
Liaw is silent upon explicitly disclosing wherein forming a first undoped semiconductor layer and a second undoped semiconductor layer, wherein the first undoped semiconductor layer partially fills the first bottom portion of the first source/drain recess and the second undoped semiconductor layer partially fills the second bottom portion of the second source/drain recess; and
forming a first doped semiconductor layer over the first undoped semiconductor layer and a second doped semiconductor over the second undoped semiconductor layer, wherein the first doped semiconductor layer fills a remainder of the first bottom portion of the first source/drain recess and the second doped semiconductor layer fills a remainder of the second bottom portion of the second source/drain recess.
For support see Jang, which teaches wherein forming a first undoped semiconductor layer (151 at the bottom surface of recess region RC) and a second undoped semiconductor layer (151 at the bottom surface of recess region RC), wherein the first undoped semiconductor layer (151 at the bottom surface of recess region RC) partially fills the first bottom portion of the first source/drain recess (RC) and the second undoped semiconductor layer (151 at the bottom surface of recess region RC) partially fills the second bottom portion of the second source/drain recess (RC) (see Jang, Figs.6 and 11K as shown above, and ¶ [0113]- ¶ [0114]); and
forming a first doped semiconductor layer (52/54) over the first undoped semiconductor layer (151 at the bottom surface of recess region RC) and a second doped semiconductor (52/54) over the second undoped semiconductor layer (151 at the bottom surface of recess region RC), wherein the first doped semiconductor layer (52/54) fills a remainder of the first bottom portion of the first source/drain recess (RC) and the second doped semiconductor layer (52/54) fills a remainder of the second bottom portion of the second source/drain recess (RC) (see Jang, Figs.6 and 11K as shown above, and ¶ [0113]- ¶ [0114]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Liaw and Jang to enable forming a first doped semiconductor layer over the first undoped semiconductor layer and a second doped semiconductor over the second undoped semiconductor layer, wherein the first doped semiconductor layer fills a remainder of the first bottom portion of the first source/drain recess and the second doped semiconductor layer fills a remainder of the second bottom portion of the second source/drain recess as taught by Jang in order to improve the electrical properties of semiconductor device.
The combination of Liaw and Jang is silent upon explicitly disclosing wherein the second depth is greater than the first depth.
For support see Lin, which teaches wherein the second depth (D3) is greater than the first depth (D4) (note: Lin teaches “the height D4 is substantially equal to the height D3. When using the term “substantially” in this specification, it means a difference equal to or less than 10%”) (see Lin, Figs.30A- 30B as shown below, ¶ [0055], and ¶ [0057]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Liaw, Jang, and Lin to enable second depth to be greater than or equal to the first depth as taught by Lin in order to increase the push-in extent of the p-type epitaxial feature.
Regarding Claim 9: Liaw as modified teaches a method as set forth in claim 8 as above. The combination of Liaw, Jang, and Lin further teaches wherein the first undoped semiconductor layer (151 at the bottom surface of recess region RC) has a first trough-shaped top surface, the second undoped semiconductor layer (151 at the bottom surface of recess region RC) has a second trough-shaped top surface (see Jang, Figs.6 and 11K as shown above).
The combination of Liaw, Jang, and Lin is silent upon explicitly disclosing wherein a first lowest point of the first trough-shaped top surface of the first undoped semiconductor layer relative to a topmost surface of the first semiconductor extension is higher than a second lowest point of the second trough-shaped top surface of the second undoped semiconductor layer relative to the topmost surface of the second semiconductor extension.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the first lowest point of the first trough-shaped top surface of the first undoped semiconductor layer relative to a topmost surface of the first semiconductor extension to be higher than a second lowest point of the second trough-shaped top surface of the second undoped semiconductor layer relative to the topmost surface of the second semiconductor extension through routine experimentation and optimization to obtain optimal or desired device performance because the first lowest point of the first trough-shaped top surface of the first undoped semiconductor layer relative to a topmost surface of the first semiconductor extension to be higher than a second lowest point of the second trough-shaped top surface of the second undoped semiconductor layer relative to the topmost surface of the second semiconductor extension is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 12: Liaw as modified teaches a method as set forth in claim 8 as above. The combination of Liaw, Jang, and Lin further teaches wherein: the forming of the first doped semiconductor layer (152/154) includes forming a first inner portion (154) having a first dopant concentration and a first outer portion (152) having a second dopant concentration, wherein the second dopant concentration (152) is less than the first dopant concentration (154) and the first outer portion of the first doped semiconductor layer (152) is between the first undoped semiconductor layer (151) and the first inner portion of the first doped semiconductor layer (154) (see Jang, Figs.6 and 11K as shown above, ¶ [0032]- ¶ [0034], ¶ [0055], and ¶¶ [0098]); and
the forming of the second doped semiconductor layer (152/154) includes forming a second doped semiconductor layer (152/154) having a second inner portion having the first dopant concentration (154) and a second outer portion having the second dopant concentration (152), wherein the second outer portion of the second doped semiconductor layer (152) is between the second undoped semiconductor layer (151) and the second inner portion of the second doped semiconductor layer (154) (see Jang, Figs.6 and 11K as shown above, ¶ [0032]- ¶ [0034], ¶ [0055], and ¶¶ [0098]).
Regarding Claim 13: Liaw as modified teaches a method as applied to claim 8 above. The combination of Liaw, Jang, and Lin is silent upon explicitly disclosing wherein the first doped semiconductor layer is coupled to a first channel layer having a first length and the second doped semiconductor layer is coupled to a second channel layer having a second length that is greater than the first length.
However, the combination of Liaw, Jang, and Lin teaches wherein the first doped semiconductor layer (152/154) is coupled to a first channel layer having a first length and the second doped semiconductor layer (152/154) is coupled to a second channel layer having a second length that is equal to the first length (see Jang, Figs.6 and 11K as shown above).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the second length with respect to the first length through routine experimentation and optimization to obtain optimal or desired device performance because the second length and the first length is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 14: Liaw as modified teaches a method as set forth in claim 8 as above. The combination of Liaw, Jang, and Lin further teaches wherein: the first device region is a memory region (see Liaw, Figs.5-7 and 11 as shown above); and
the second device region is an input/output region (see Liaw, Figs.5-7 and 11 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Claim(s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (U.S. 2021/0066452 A1, hereinafter refer to Liaw) and Jang et al. (U.S. 2020/0220018 A1, hereinafter refer to Jang) as applied to claim 1 above, and Son et al. (U.S. 2020/0303521 A1, hereinafter refer to Son).
Regarding Claim 3: Liaw as modified teaches a method as applied to claim 1 above. The combination of Liaw and Jang is silent upon explicitly disclosing wherein the forming the first undoped epitaxial layer and the second undoped epitaxial layer includes performing a selective chemical vapor deposition process and performing an etching process after the selective chemical vapor deposition process.
For support see Son, which teaches wherein the forming the first undoped epitaxial layer (132) and the second undoped epitaxial layer (132) includes performing a selective chemical vapor deposition process and performing an etching process after the selective chemical vapor deposition process (an epitaxial growth process using the gas including Si and/or the gas including Ge and an etching process using an hydrochloric acid (HCl) gas or chlorine (Cl2) gas as an etching gas may be performed) (see Son, Figs.18-19, ¶ [0036], and ¶ [0119] -¶ [0120]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings Liaw, Jang, and Son to enable the known performing a selective chemical vapor deposition process and performing an etching process after the selective chemical vapor deposition process for forming undoped epitaxial layer of the combination of Liaw and Jang as taught by Son because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed undoped epitaxial layer and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 4: Liaw as modified teaches a method as set forth in claim 1 as above. The combination of Liaw, Jang, and Son further teaches wherein the performing the selective chemical vapor deposition process and the performing the etching process are performed in-situ (see Son, Figs.18-19, ¶ [0036], and ¶ [0119] -¶ [0120]).
Claim(s) 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (U.S. 2021/0066452 A1, hereinafter refer to Liaw), Jang et al. (U.S. 2020/0220018 A1, hereinafter refer to Jang), and Lin et al. (U.S. 2021/0098311 A1, hereinafter refer to Lin) as applied to claim 8 above, and further in view of Son et al. (U.S. 2020/0303521 A1, hereinafter refer to Son).
Regarding Claim 15: Liaw as modified teaches a method as applied to claim 8 above. The combination of Liaw, Jang, and Lin is silent upon explicitly disclosing wherein the forming of the first undoped semiconductor layer and the second undoped semiconductor layer includes:
performing a selective chemical vapor deposition process to form silicon-comprising material that partially fills the first source/drain recess and the second source/drain recess; and
performing an etching process after the selective chemical vapor deposition process.
For support see Son, which teaches wherein the forming of the first undoped semiconductor layer (132) and the second undoped semiconductor layer (132) (see Son, Figs.18-19, ¶ [0036], and ¶ [0119] -¶ [0120]) includes:
performing a selective chemical vapor deposition process to form silicon-comprising material that partially fills the first source/drain recess and the second source/drain recess (n epitaxial growth process using the gas including Si and/or the gas including Ge and an etching process using an hydrochloric acid (HCl) gas or chlorine (Cl2) gas as an etching gas may be performed) (see Son, Figs.18-19, ¶ [0036], and ¶ [0119] -¶ [0120]); and
performing an etching process after the selective chemical vapor deposition process (note: epitaxial growth process using the gas including Si and/or the gas including Ge and an etching process using an hydrochloric acid (HCl) gas or chlorine (Cl2) gas as an etching gas may be performed) (see Son, Figs.18-19, ¶ [0036], and ¶ [0119] -¶ [0120]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings Liaw, Jang, Lin, and Son to enable the known performing a selective chemical vapor deposition process and performing an etching process after the selective chemical vapor deposition process for forming undoped epitaxial layer of the combination of Liaw and Jang as taught by Son because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed undoped epitaxial layer and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 16: Liaw as modified teaches a method as set forth in claim 15 as above. The combination of Liaw, Jang, Lin, and Son further teaches wherein vacuum is not broken between performing the selective chemical vapor deposition process and performing the etching process (see Son, Figs.18-19, ¶ [0036], and ¶ [0119] -¶ [0120]).
Claim(s) 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (U.S. 2020/0220018 A1, hereinafter refer to Jang) as applied to claim 17 above, and further in view of Liaw (U.S. 2021/0066452 A1, hereinafter refer to Liaw).
Regarding Claim 19: Jang discloses a method as applied to claim 17 above. Jang further reaches wherein: the semiconductor layer stack has a height; and
provide the first depth less than the height when the size of the active region is less than the threshold width (see Jang, Figs.6 and 11K as shown above).
Jang is silent upon explicitly disclosing wherein the forming of the source/drain recesses is tuned to provide the first depth greater than the height when the size of the active region is greater than a threshold width.
For support see Liaw, which teaches wherein: the semiconductor layer stack (251/261) has a height; and
the forming of the source/drain recesses (133) is tuned to provide the first depth (height plus D1) greater than the height when the size of the active region is greater than a threshold width (W1) (see Liaw, Fig.5 as shown above and ¶ [0111]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Jang and Liaw to enable forming of the source/drain recesses to be tuned to provide the first depth greater than the height when the size of the active region is greater than a threshold width as taught by Liaw in order to improve ION performance as well as increased connection margin for the source/drain to bottom sheet ends.
Regarding Claim 20: Jang as modified teaches a method as set forth in claim 19 as above. The combination of Jang and Liaw further teaches wherein the threshold width (W1) is about 30 nm (see Liaw, Fig.5 as shown above and ¶ [0044]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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