Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office action is in response to a preliminary amendment filed on10/15/2024. This application is a continuation of parent application no. 17/881,984, which is a divisional of application no. 16/872,551.
Currently, claims 21-40 are pending and examined below.
Information Disclosure Statement (IDS)
Applicant submitted four information disclosure statements on 07/25/2024 ("07-25-24 IDS"), 10/18/2024 ("10-18-24 IDS"), 01/29/2025 (“01-29-25 IDS”) and 05/28/2025 (“05-28-25 IDS”). Since the Applicant has met the provisions of 37 CFR 1.97, the 07-25-24 IDS, 10-18-24 IDS, 01-29-25 IDS and 05-28-25 IDS are in compliance and are being considered by the examiner.
Specification
The specification is objected to, because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: METHOD FOR FORMING AN INTEGRATED CHIP HAVING BARRIER STRUCTURE CONFIGURED TO INCREASE PERFORMANCE OF III-V DEVICES
A. Prior-art rejections based on Yeh
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21, 22, 27 and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2018/0026106 A1 to Yeh et al. (“Yeh").
Fig. 2A of Yeh is provided to support the rejections below:
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Regarding independent claim 21, Yeh teaches a method for forming an integrated chip (see Fig. 2A; see also Fig. 1B for example), the method comprising: comprising:
depositing a semiconductor layer 114 (para [0020] - “In some embodiments, the channel layer 114 is a group III-V material and/or is undoped. For example, the channel layer 114 may be undoped gallium nitride (u-GaN).”) over a substrate 130 (para [0025] - “As illustrated, a substrate 130 supports the channel layer 114 with a buffer layer 132 arranged between the substrate 130 and the channel layer 114.”);
depositing a first barrier layer 118 on the semiconductor layer 114, wherein the first barrier layer 118 comprises a semiconductor material InyAlzG1-y-zN with a first concentration of elements (para [0019] - “In some embodiments, the upper and lower barrier layers 116, 118 are compounds of the same elements, but with different ratios of the elements, and/or are group III-V nitrides or some other group III-V compounds. For example, the upper and lower barrier layers 116, 118 may respectively be InwAlxG1-x-wN and InyAlzG1-y-zN, where w, x, y, and z are each between 0 and 1.”);
forming a doped layer 110a and/or 110b (para [0027] - “The multiple gate dielectric layers 110a, 110b, 110c comprise a group III nitride, silicon dioxide, silicon nitride, or a combination of the foregoing, and/or are doped with p-type or n-type dopants. For example, the first and third gate dielectric layers 110a, 110c may be p-type GaN, and the second gate dielectric layer 110b may be n-type gallium nitride (n-GaN). “) on the first barrier layer 118; and
forming a second barrier layer 116 on the first barrier layer 118 and laterally offset from the doped layer 110a and/or 110b, wherein the second barrier layer 116 comprises the semiconductor material InwAlxG1-x-wN with a second concentration of elements different from the first concentration of elements (para [0019] - “…different ratios of the elements…”), wherein a bottom surface of the second barrier layer 116 is disposed below a bottom surface of the doped layer 110a and/or 110b and above a bottom surface of the first barrier layer 116.
Regarding claim 22, Yeh teaches a vertical distance (in the L region of the gate opening 112) between the bottom surface of the second barrier layer 116 and a top surface of the first barrier layer 118 is less than a first thickness T2 of the first barrier layer 118 directly below the bottom surface of the second barrier layer 116.
Regarding claim 27, Yeh teaches a first sidewall of the second barrier layer 116 facing the doped layer 110a and/or 110b is laterally offset from the doped layer 110a and/or 110b by a lateral distance greater than a width of the doped layer 110a.
Regarding independent claim 30, Yeh teaches a method for forming an integrated chip, the method comprising:
depositing a semiconductor layer 114 over a substrate 130;
depositing a first barrier layer 118 on the semiconductor layer 114;
forming a doped layer 110a and/or 110b on the first barrier layer 118; and
forming a second barrier layer 116 on the first barrier layer 118 by a selective deposition process (see Figs. 4 and 5), wherein the second barrier layer 118 is arranged in a peripheral region laterally offset from the doped layer 110a and/or 110b, wherein at least a portion of the first barrier layer 118 in the peripheral region is removed during the selective deposition process (see Fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
(1). Determining the scope and contents of the prior art.
(2). Ascertaining the differences between the prior art and the claims at issue.
(3). Resolving the level of ordinary skill in the pertinent art.
(4). Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh.
Regarding claim 24, Yeh does not specifically disclose a particular thickness of the second barrier layer being within a range of 0.5 to 3 nanometers, so Yeh does not teach the vertical distance (i.e., depression from the top of layer 118 in the gate opening 112) being within a range of 0.5 to 3 nanometers.
However, in Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Court held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04).
Since the only difference between the claimed method and the method taught by Yeh is a relative dimension of the vertical distance being within a range of 0.5 to 3 nanometers, the Court would be more likely than not hold that the claimed method is not patentably distinct from the method taught by Yeh. Moreover, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art modify the method such that vertical distance is within a range of 0.5 to 3 nanometers with a reasonable expectation of providing an integrated chip that is in the nanometer scale as the one of ordinary skill in the semiconductor art is incentivized to make adjustments to size to fit an intended purpose of making device smaller as market forces demand that the device scale down with Moore's Law.
B. Prior-art rejections based on Chen
Claim Rejections - 35 USC § 1022
Claims 30 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2020/0127116 A1 to Chen et al. (“Chen”).
Fig. 2 of Chen has been provided to support the rejections below:
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Regarding independent claim 30, Chen teaches a method for forming an integrated chip, the method comprising:
depositing a semiconductor layer 106 over a substrate 102 (para [0018] - “A buffer layer 104 is formed over the substrate 102, a channel layer 106 is formed over the buffer layer 104, and a barrier layer 108 is formed over the channel layer 106.”);
depositing a first barrier layer 108 (para [0048] - “In the embodiments shown in FIG. 2, the lining layer 118 is conformally disposed between the bottom portions of the source/drain electrodes 120 and the barrier layer 108 thereby enhancing the spontaneous polarization and the piezoelectric polarization between the lining layer 118 and the channel layer 106.”) on the semiconductor layer 106
forming a doped layer 110 (para [0050] - “doped compound semiconductor block 110”) on the first barrier layer 108; and
forming a second barrier layer 118 (para [0054] - “The lining layer 118 formed on the sidewalls of the doped compound semiconductor block 110 can repaid the lattice defects on the sidewalls of the doped compound semiconductor block 110 to reduce the gate leak current of the resulting semiconductor device.”; that is, the lining layer 118 helps to block or functions as a barrier to reduce gate leakage current.) on the first barrier layer 108 by a selective deposition process (see Figs. 3A-3C), wherein the second barrier layer 118 is arranged in a peripheral region laterally offset from the doped layer 110, wherein at least a portion of the first barrier layer 108 in the peripheral region 116 is removed during the selective deposition process (see Fig. 3C).
Regarding claim 31, Chen teaches a first thickness of the first barrier layer 108 under the doped layer remains constant during the selective deposition process, wherein a second thickness of the first barrier layer 108 in the peripheral region 116 is less than the first thickness (see Fig. 3C).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 23 is objected to for depending on a rejected base claim 21 and the intervening claim 22, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 21 and the intervening claim 22 or the base claim 21 is amended to include all of the limitations of claim 23 and the intervening claim 22.
Claim 25 is objected to for depending on a rejected base claim 21, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 21 or the base claim 21 is amended to include all of the limitations of claim 25.
Claim 26 is allowable, because it depends from the allowable claim 25.
Claim 28 is objected to for depending on a rejected base claim 21 and the intervening claim 27, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 21 and the intervening claim 27 or the base claim 21 is amended to include all of the limitations of claim 28 and the intervening claim 27.
Claim 29 is objected to for depending on a rejected base claim 21 and the intervening claim 27, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 21 and the intervening claim 27 or the base claim 21 is amended to include all of the limitations of claim 29 and the intervening claim 27.
Claim 32 is objected to for depending on a rejected base claim 30 and the intervening claim 31, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 30 and the intervening claim 31 or the base claim 30 is amended to include all of the limitations of claim 32 and the intervening claim 31.
Claim 35 is objected to for depending on a rejected base claim 30, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 30 or the base claim 30 is amended to include all of the limitations of claim 35.
Claim 36 is allowable, because it depends from the allowable claim 35.
Independent claim 37 is allowed, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 37, wherein a concentration of the first element in the barrier structure discretely increases at a first sidewall of the opposing sidewalls of the second barrier layer, wherein the first sidewall of the second barrier layer is spaced laterally between the doped layer and a first contact structure in the pair of contact structures.
Claims 38-40 are allowed, because they depend from the allowed independent claim 37.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2020/0373297 A1 to Nidhi et al.
Pub. No. US 2017/0330944 A1 to Baines et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano, can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2817 21 September 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
2 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
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