DETAILED ACTION
Allowable Subject Matter
Claims 21-24 are allowed.
The following is an examiner’s statement of reasons for allowance.
Claim 21 recites in part “wherein the conductive core comprises a first segment over a second segment, wherein a width of the first segment continuously increases across a first vertical distance, wherein a width of the second segment continuously decreases across a second vertical distance, wherein the second vertical distance is greater than the first vertical distance”.
To elaborate briefly on the above, this case is a divisional of previously allowed “method of making” case (S/N 17/353,003). In that case, the allowable subject matter was very similar to the limitations cited above, just worded differently. Hence, claim 21 is allowable over cited prior art for virtually the same reasons as those in parent case.
Claims 7 & 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter. The limitations of claim 7 (that the core of the “isolation structure” receives its bias specifically from “conductive grid structure”) is not found in the cited prior art.
Claim 13 recites limitations that require similar structure and therefore are indicated as allowable for similar reasons.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4 & 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US-2017/0062496) by Lai et al (“Lai”).
Regarding claim 1, Lai discloses in FIGs. 1-16 and related text, e.g., an image sensor, comprising:
a semiconductor substrate (FIG. 16, 102) comprising a front-side surface (bottom) opposite a back-side surface (top);
a plurality of photodetectors (104) disposed in the semiconductor substrate; and
an isolation structure (144) extending into the back-side surface of the semiconductor substrate and disposed between adjacent photodetectors, wherein the isolation structure includes a metal core (142B), a conductive liner (142A) disposed between the semiconductor substrate and the metal core, and a first dielectric liner (132) disposed between the conductive liner and the semiconductor substrate, wherein the metal core comprises a first metal material (par. 32: “conductive layer 142B may comprise … other opaque or reflective (e.g., metallic) materials …; in the instant case, Ti; it is a, to degree, reflective material) and the conductive liner comprises the first metal material and a second metal material different from the first metal material (par. 32, 142A is “titanium nitride”; thus meeting limitations).
Regarding claim 2, Lai discloses in FIGs. 1-16 and related text, e.g., wherein a width of the metal core continuously increases from the back-side surface to a first point disposed below the back-side surface, and wherein the width of the metal core continuously decreases from the first point to a second point disposed below the first point (see the shape of 142B; it meets limitations exactly).
Regarding claim 4, Lai discloses in FIGs. 1-16 and related text, e.g., further comprising: a second dielectric liner (140; silicon oxide; par. 31) disposed between the first dielectric liner and the conductive liner, wherein the first dielectric liner has a first dielectric constant greater than a second dielectric constant of the second dielectric liner (132 comprises high-k dielectrics; see par. 27; 140 does not; hence, meeting limitations).
Regarding claim 5, Lai discloses in FIGs. 1-16 and related text, e.g., further comprising: a conductive grid structure (FIG. 15, 148) overlying the front-side surface of the semiconductor substrate, wherein the conductive grid structure directly overlies and is aligned with the metal core (see par. 35, and FIG. 14B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 9, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2017/0062496) by Lai et al (“Lai”).
Regarding claim 6, Lai discloses in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, except “further comprising: a bias circuit electrically coupled to the isolation structure and configured to apply a negative bias to the metal core”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Lai with “further comprising: a bias circuit electrically coupled to the isolation structure and configured to apply a negative bias to the metal core”, in order to have a properly functioning computer chip, since leaving an un-biased metal core would result a rise of parasitic capacitance issues; therefore, benefitting from tying off of metal core to negative bias (aka, “ground”).
Regarding claim 9, Lai discloses in FIGs. 1-16 and related text, e.g., an image sensor, comprising:
a semiconductor substrate comprising sidewalls that define a trench (122);
a plurality of photodetectors disposed laterally within a pixel array region of the semiconductor substrate (see claim 1 and FIG. 14B);
an isolation structure disposed within the trench of the semiconductor substrate, wherein the isolation structure laterally encloses the plurality of photodetectors (see claim 1 and FIG. 14B), wherein the isolation structure comprises a metal core and a conductive liner disposed between the sidewalls of the semiconductor substrate defining the trench and the metal core (see claim 1);
a metal grid structure overlying the isolation structure (see claim 5); and
a bias circuit electrically coupled to the metal core and configured to apply a bias voltage to the metal core (see claim 6).
Regarding claim 15, Lai discloses in FIGs. 1-16 and related text, e.g., further comprising: a first dielectric liner (see claim 1) disposed between the conductive liner and the semiconductor substrate, wherein the first dielectric liner comprises a first dielectric layer (132) and a second dielectric layer (140), wherein the first dielectric layer lines (see FIG. 16) the sidewalls of the semiconductor substrate that define the trench, wherein the second dielectric layer continuously extends from a back-side surface of the semiconductor substrate to an inner sidewall of the first dielectric layer (see FIG. 16).
Regarding claim 16, Lai discloses in FIGs. 1-16 and related text, e.g., wherein a top surface of the first dielectric layer is vertically aligned with the back-side surface of the semiconductor substrate (see FIG. 16).
Claims 3 & 14 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2017/0062496) by Lai et al (“Lai”) in view of (US-2021/0288086) by Li et al (“Li”).
Regarding claim 3, Lai discloses in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, except “wherein the first metal material comprises aluminum and the second metal material comprises titanium and carbon“.
Li discloses in FIG. 3G and related text, e.g., “wherein the first metal material comprises aluminum (claim 18) and the second metal material comprises titanium and carbon (claim 17).“
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Lai with “wherein the first metal material comprises aluminum and the second metal material comprises titanium and carbon“ as taught by Li, since applying a known technique (technique of Li, for forming deep trench isolation for image sensors (par. 3, etc.)) to a known device ready for improvement (device of Lai who also deals with deep trench isolation and image sensors) to yield predictable results (results are predictable since both inventions deal with deep trenches and have those deep trenches applied to image sensors), resulting in improved system (as is notoriously well-known the two types of materials have very different material properties; therefore, depending on which of the two types of material properties are preferred in a given design, a given set of materials will be preferred; thus, resulting in an improved system, in a case where material properties of a second type of materials are more preferred) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Regarding claim 14, the combined device of Lai and Li disclose in cited figures and related text, e.g., wherein the metal core consists essentially of aluminum and the conductive liner comprises titanium aluminum carbide (see claim 3).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over (US-2017/0062496) by Lai et al (“Lai”) in view of (US-2020/0006410) by Wu et al (“Wu”).
Regarding claim 8, Lai discloses in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, except “wherein the metal core comprises sidewalls defining a void, wherein the void is spaced laterally between opposing sidewalls of the conductive liner“.
Wu discloses in FIG. 12 and related text, e.g., “wherein the metal core (68) comprises sidewalls defining a void (64), wherein the void is spaced laterally between opposing sidewalls of the conductive liner (in a combined device; since Lai has such “conductive liner” on the outside of “metal core”)“.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Lai with “wherein the metal core comprises sidewalls defining a void, wherein the void is spaced laterally between opposing sidewalls of the conductive liner“ as taught by Wu, in order to improve the quantum efficiency of image sensor (par. 15).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2017/0062496) by Lai et al (“Lai”) in view of (US-9,871,070) by Hsu et al (“Hsu”).
Regarding claim 10, Lai discloses in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, except “a through substrate via (TSV) disposed within a peripheral region of the semiconductor substrate, wherein the peripheral region is laterally offset from the pixel array region, and wherein the metal core is electrically coupled to the TSV”.
Hsu discloses in FIG. 1 and related text, e.g., “a through substrate via (TSV) (FIG. 1, 124) disposed within a peripheral region of the semiconductor substrate (see FIG. 1), wherein the peripheral region is laterally offset from the pixel array region (contains 120’s), and wherein the metal core is electrically coupled to the TSV (as was discussed in claim 9, it is necessary to connect the core to “negative bias” (aka ground); TSVs in Hsu’s case provides outside connections for the integrated circuit; one type of outside connection that is notoriously well-known in the art is a ground bias connection; hence, the above limitations are at the very least obvious in light of Hsu’s explicit teachings)“.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Lai with “a through substrate via (TSV) disposed within a peripheral region of the semiconductor substrate, wherein the peripheral region is laterally offset from the pixel array region, and wherein the metal core is electrically coupled to the TSV” as taught by Hsu, in order to have an outside connection for the overall device (this is the purpose of TSV 124) and in order to minimize leakage current, etc. (col. 2, lines 65-68).
Regarding claim 11, Lai and Hsu disclose in cited figures and related text, e.g., an upper conductive structure (130) disposed laterally within the peripheral region, wherein the bias circuit is electrically coupled to the metal core (FIG. 138; it is “metal core” in combined device, since that is what Lai teaches) by way of the TSV and the upper conductive structure (see FIG. 1).
Regarding claim 12, Lai and Hsu disclose in cited figures and related text, e.g., wherein the metal core continuously laterally extends from the pixel array region to the peripheral region (see FIG. 1, right most 138 is in peripheral region, since it does not have 120 to the right of it; it “continuously laterally extends” to that peripheral region) and directly contacts the upper conductive structure (see FIG. 1)
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
08/08/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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