DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/19/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 5-20 of U.S. Patent No. 12,148,745. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 1, Pat '745 discloses, in claim 9, an integrated circuit, comprising:
a first standard cell spanning a first dimension DL along a first direction from a first cell edge to a second cell edge, and spanning from a third cell edge to a fourth cell edge along a second direction being orthogonal to the first direction, wherein the first standard cell includes a first, second, third and fourth active regions longitudinally oriented in the second direction; a second standard cell spanning a second dimension DS along the first direction from a fifth cell edge to a sixth cell edge, and spanning from a seventh cell edge to an eighth cell edge along the second direction, wherein the second standard cell includes a fifth and sixth active regions longitudinally oriented in the second direction (all limitations are the same with the limitations recited in claim 9 of Pat '745); and
gate stacks oriented along the first direction and continuously extend from the sixth cell edge of the second standard cell to the first cell edge of the first standard cell ("a plurality of gate stacks oriented along the first direction and continuously extend from the sixth cell edge of the second standard cell to the first cell edge of the first standard cell", in claim 9 of Pat '745, is interpreted as the same limitation), wherein one of the first, second, third and fourth active regions includes a plurality of segments aligned and spaced away from each other along the second direction, and the fifth and sixth active regions continuously extend from the seventh cell edge to the eighth cell edge along the second direction (all limitations are the same with the limitations recited in claim 9 of Pat '745).
Regarding claim 2, Pat '745 discloses the integrated circuit of claim 1 as described above.
Pat '745 further discloses, in claims 9 and 14, each of the first, second, third, fourth, fifth, and sixth active regions includes multiple channels vertically stacked; each of the multiple channels has a same thickness T, T being substantially equal to W; and the second dimension DS is less than the first dimension DL (all limitations are the same with the limitations recited in claims 9 and 14 of Pat '745).
Regarding claim 3, Pat '745 discloses the integrated circuit of claim 2 as described above.
Pat '745 further discloses, in claim 14, each of the gate stacks laterally extends over the each of the first, second, third, fourth, fifth and sixth active regions and vertically extends down to surround each of the channels (all limitations are the same with the limitations recited in claim 14 of Pat '745).
Regarding claim 4, Pat '745 discloses the integrated circuit of claim 1 as described above.
Pat '745 further discloses, in claim 10, the first and second active regions are spaced away from the third and fourth active regions with a first spacing S1 along the first direction; the first active region and the second active region are spaced away with a second spacing S2 therebetween along the first direction; and S1 being greater than S2 (all limitations are the same with the limitations recited in claim 10 of Pat '745).
Regarding claim 5, Pat '745 discloses the integrated circuit of claim 4 as described above.
Pat '745 further discloses, in claims 10 and 11, the fifth and sixth active regions are spaced away with the first spacing S1 therebetween along the first direction; the third active region and the fourth active region are spaced away with the second spacing S2 therebetween along the first direction; and the fifth cell edge continuously contacts the second cell edge (all limitations are the same with the limitations recited in claims 10 and 11 of Pat '745).
Regarding claim 6, Pat '745 discloses the integrated circuit of claim 1 as described above.
Pat '745 further discloses, in claim 11, the first standard cell spans a third dimension LL from the third cell edge to the fourth cell edge along the second direction; the second standard cell spans a fourth dimension LS from the seventh cell edge to the eighth cell edge along the second direction; and LL is equal to LS (all limitations are the same with the limitations recited in claim 11 of Pat '745).
Regarding claim 7, Pat '745 discloses the integrated circuit of claim 1 as described above.
Pat '745 further discloses, in claim 12, the third cell edge is aligned with the seventh cell edge along the first direction; and the fourth cell edge is aligned with the eighth cell edge along the first direction (all limitations are the same with the limitations recited in claim 12 of Pat '745).
Regarding claim 8, Pat '745 discloses the integrated circuit of claim 1 as described above.
Pat '745 further discloses, in claim 13, the first, second, third, fourth, fifth, and sixth active regions have a same width W spanning along the first direction (all limitations are the same with the limitations recited in claim 13 of Pat '745).
Regarding claim 9, Pat '745 discloses the integrated circuit of claim 1 as described above.
Pat '745 further discloses, in claim 13, the gate stacks include a first gate stack extending on the third and seventh cell edges, and a second gate stack extending on the fourth and eighth cell edges ("the plurality of gate stacks includes a first gate stack extending on the third and seventh cell edges, and a second gate stack extending on the fourth and eighth cell edges", in claim 13 of Pat '745, is interpreted as the same limitation).
Regarding claim 10, Pat '745 discloses the integrated circuit of claim 1 as described above.
Pat '745 further discloses, in claim 15, a first p-type field-effect transistor (pFET) device formed on the first and second active regions; a second pFET device formed on the sixth active region; a first n-type field-effect transistor (nFET) device formed on the third and fourth active regions; and a second nFET device formed on the fifth active region (all limitations are the same with the limitations recited in claim 15 of Pat '745).
Regarding claim 11, Pat '745 discloses, in claim 16, an integrated circuit, comprising:
a first standard cell spanning a first dimension L1 along a first direction from a first cell edge to a second cell edge and spanning a second dimension L2 from a third cell edge to a fourth cell edge along a second direction being orthogonal to the first direction, wherein the first standard cell includes first active regions oriented along the second direction, and wherein the first active regions are configured with a first spacing S1 therebetween, and second active regions oriented along the second direction, and wherein the second active regions are configured with the first spacing S1 therebetween, wherein the first active regions are spaced away from the second active regions with a second spacing S2, wherein S2 is greater than S1 (all limitations are the same with the limitations recited in claim 16 of Pat '745);
a second standard cell spanning a third dimension L3 along the first direction from a fifth cell edge to a sixth cell edge and spanning a fourth dimension L4 from a seventh cell edge to an eighth cell edge along the second direction, wherein the second standard cell includes a third active region and a fourth active region spanning from the seventh cell edge to the eighth cell edge along the second direction, wherein the third active region and the fourth active region are spaced away with a third spacing S3 therebetween, wherein S3 is equal to S2, and wherein the second standard cell is disposed such that the fifth cell edge is aligned with and contacts the second cell edge (all limitations are the same with the limitations recited in claim 16 of Pat '745); and
gate stacks oriented along the first direction and continuously extend from the sixth cell edge of the second standard cell to the first cell edge of the first standard cell ("a plurality of gate stacks oriented along the first direction and continuously extend from the sixth cell edge of the second standard cell to the first cell edge of the first standard cell", in claim 16 of Pat '745, is interpreted as the same limitation).
Regarding claim 12, Pat '745 discloses the integrated circuit of claim 11 as described above.
Pat '745 further discloses, in claim 17, the first active regions, the second active regions, the third active region and the fourth active region have a same width W spanning along the first direction; and the second standard cell is disposed such that the third cell edge is aligned with the seventh cell edge and the fourth cell edge is aligned with the eighth cell edge (all limitations are the same with the limitations recited in claim 17 of Pat '745).
Regarding claim 13, Pat '745 discloses the integrated circuit of claim 11 as described above.
Pat '745 further discloses, in claim 18, each of the first active regions, the second active regions, the third active region and the fourth active region includes multiple channels vertically stacked, and wherein each of the multiple channels has a same thickness T, T being substantially equal to W (all limitations are the same with the limitations recited in claim 18 of Pat '745).
Regarding claim 14, Pat '745 discloses the integrated circuit of claim 13 as described above.
Pat '745 further discloses, in claim 19, each of the gate stacks laterally extends over the each of the first active regions, the second active regions, the third active region and the fourth active region, and vertically extends down to surround each of the channels (all limitations are the same with the limitations recited in claim 19 of Pat '745).
Regarding claim 15, Pat '745 discloses the integrated circuit of claim 13 as described above.
Pat '745 further discloses, in claim 16, L3 is less than L1 and L4 is equal to L2 (all limitations are the same with the limitations recited in claim 16 of Pat '745).
Regarding claim 20, Pat '745 discloses the integrated circuit of claim 11 as described above.
Pat '745 further discloses, in claim 20, a first p-type field-effect transistor (pFET) device formed on the first active regions; a second pFET device formed on the fourth active region; a first n-type field-effect transistor (nFET) device formed on the second active regions; and a second nFET device formed on the third active region, wherein the gate stacks includes a first gate stack aligned with and extending on the third and seventh cell edges, and a second gate stack aligned with and extending on the fourth and eighth cell edges (all limitations are the same with the limitations recited in claim 20 of Pat '745).
Regarding claim 17, Pat '745 discloses, in claim 1, an integrated circuit, comprising:
a first standard cell spanning a first dimension L1 along a first direction from a first cell edge to a second cell edge and spanning a second dimension L2 from a third cell edge to a fourth cell edge along a second direction being orthogonal to the first direction, wherein the first standard cell includes a first active region and a second active region oriented along the second direction, and wherein the first active region and the second active region are spaced away with a first spacing S1 therebetween (all limitations are the same with the limitations recited in claim 1 of Pat '745);
a second standard cell spanning a third dimension L3 along the first direction from a fifth cell edge to a sixth cell edge and spanning a fourth dimension L4 from a seventh cell edge to an eighth cell edge along the second direction, wherein the second standard cell includes a third active region and a fourth active region spanning from the seventh cell edge to the eighth cell edge along the second direction, wherein the third active region and the fourth active region are spaced away with a second spacing S2 therebetween, wherein S2 is equal to S1, wherein L3 is less than L1, and wherein the second standard cell is disposed such that the fifth cell edge is overlapped with the second cell edge (all limitations are the same with the limitations recited in claim 1 of Pat '745); and
gate stacks oriented along the first direction and continuously extend from the sixth cell edge of the second standard cell to the first cell edge of the first standard cell ("a plurality of gate stacks oriented along the first direction and continuously extend from the sixth cell edge of the second standard cell to the first cell edge of the first standard cell", in claim 1 of Pat '745, is interpreted as the same limitation).
Regarding claim 18, Pat '745 discloses the integrated circuit of claim 17 as described above.
Pat '745 further discloses, in claim 8, each of the first and second active regions includes a plurality of segments aligned and spaced away from each other along the second direction; and each of the third and fourth active regions continuously extend from the seventh cell edge to the eighth cell edge along the second direction (all limitations are the same with the limitations recited in claim 8 of Pat '745).
Regarding claim 19, Pat '745 discloses the integrated circuit of claim 17 as described above.
Pat '745 further discloses, in claims 2, 3, and 7, the second standard cell is disposed such that the third cell edge is aligned with the seventh cell edge and the fourth cell edge is aligned with the eighth cell edge; each of the first, second, third and fourth active regions includes multiple channels vertically stacked; each of the gate stacks laterally extends over the each of the first, second, third and fourth active regions and vertically extends down to surround each of the channels; and the gate stacks include a first gate stack extending on the third and seventh cell edges, and a second gate stack on the fourth and eighth cell edges (all limitations are the same with the limitations recited in claims 2, 3, and 7 of Pat '745).
Regarding claim 20, Pat '745 discloses the integrated circuit of claim 17 as described above.
Pat '745 further discloses, in claims 1, 5, and 6, the first, second, third and fourth active regions span a first width W1, a second width W2, a third width W3, and a fourth width W4, respectively, along the first direction; W2 is greater than W1; W3 is greater than W4; W2/ W1 is greater than 1.5, and W3/W4 is greater than 1.5; and L4 is equal to L2 (all limitations are the same with the limitations recited in claims 1, 5, and 6 of Pat '745).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 6-9 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Li (US 2020/0104446).
Regarding claim 1, Li discloses, in at least figures 2A-2B, 6, and related text, an integrated circuit, comprising:
a first standard cell (230, [35]) spanning a first dimension DL along a first direction (cell height, figures) from a first cell edge (upper edge of 230, figures) to a second cell edge (lower edge of 230, figures), and spanning from a third cell edge (left edge of 230, figures) to a fourth cell edge (right edge of 230, figures) along a second direction (cell width, figures) being orthogonal to the first direction (cell height, figures), wherein the first standard cell (230, [35]) includes a first (upper OD-P type, [20], [56], figures), second (upper OD-N type, [20], [56], figures), third (lower OD-N type, [20], [56], figures) and fourth (lower OD-P type, [20], [56], figures) active regions longitudinally oriented in the second direction (cell width, figures);
a second standard cell (220, [35]) spanning a second dimension DS along the first direction (cell height, figures) from a fifth cell edge (upper edge of 220, figures) to a sixth cell edge (lower edge of 220, figures), and spanning from a seventh cell edge (left edge of 220, figures) to an eighth cell edge (right edge of 220, figures) along the second direction (cell width, figures), wherein the second standard cell (220, [35]) includes a fifth (OD-P type, [20], [56], figures) and sixth (OD-N type, [20], [56], figures) active regions longitudinally oriented in the second direction (cell width, figures); and
gate stacks (Poly, [20], [56], figures) oriented along the first direction (cell height, figures) and continuously extend from the sixth cell edge (lower edge of 220, figures) of the second standard cell (220, [35]) to the first cell edge (upper edge of 230, figures) of the first standard cell (230, [35]), wherein
one of the first (upper OD-P type, [20], [56], figures), second (upper OD-N type, [20], [56], figures), third (lower OD-N type, [20], [56], figures) and fourth (lower OD-P type, [20], [56], figures) active regions includes a plurality of segments aligned and spaced away from each other along the second direction (cell width, figures), and
the fifth (OD-P type, [20], [56], figures) and sixth (OD-N type, [20], [56], figures) active regions continuously extend from the seventh cell edge (left edge of 220, figures) to the eighth cell edge (right edge of 220, figures) along the second direction (cell width, figures).
Regarding claim 6, Li discloses the integrated circuit of claim 1 as described above.
Li further discloses, in at least figures 2A-2B, 6, and related text, the first standard cell (230, [35]) spans a third dimension LL from the third cell edge (left edge of 230, figures) to the fourth cell edge (right edge of 230, figures) along the second direction (cell width, figures); the second standard cell (220, [35]) spans a fourth dimension LS from the seventh cell edge (left edge of 220, figures) to the eighth cell edge (right edge of 220, figures) along the second direction (cell width, figures); and LL is equal to LS (figures).
Regarding claim 7, Li discloses the integrated circuit of claim 1 as described above.
Li further discloses, in at least figures 2A-2B, 6, and related text, the third cell edge (left edge of 230, figures) is aligned with the seventh cell edge (left edge of 220, figures) along the first direction (cell height, figures); and the fourth cell edge (right edge of 230, figures) is aligned with the eighth cell edge (right edge of 220, figures) along the first direction (cell height, figures).
Regarding claim 8, Li discloses the integrated circuit of claim 1 as described above.
Li further discloses, in at least figures 2A-2B, 6, and related text, the first (upper OD-P type, [20], [56], figures), second (upper OD-N type, [20], [56], figures), third (lower OD-N type, [20], [56], figures), fourth (lower OD-P type, [20], [56], figures), fifth (OD-P type, [20], [56], figures), and sixth (OD-N type, [20], [56], figures) active regions have a same width W spanning along the first direction (cell height, figures).
Regarding claim 9, Li discloses the integrated circuit of claim 1 as described above.
Li further discloses, in at least figures 2A-2B, 6, and related text, the gate stacks (Poly, [20], [56], figures) include a first gate stack extending on the third (left edge of 230, figures) and seventh (left edge of 220, figures) cell edges, and a second gate stack extending on the fourth (right edge of 230, figures) and eighth (right edge of 220, figures) cell edges.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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