Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7, 9-10 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsieh et al. (US 9620582).
Regarding claim 1, Hsieh discloses a capacitor structure, comprising:
one or more lower interconnects (103a/103b, 105a/105b) disposed within a lower dielectric structure (102a/102b) over a substrate (101) [Fig. 1B];
a lower electrode (106) arranged along sidewalls (111) and an upper surface (102s) of the lower dielectric structure (102b) [Fig. 1B];
a capacitor dielectric (108) arranged along sidewalls and an upper surface of the lower electrode [Fig. 1B];
an upper electrode (110) arranged along sidewalls and an upper surface of the capacitor dielectric [Fig. 1B]; and
a spacer (114) arranged along outermost sidewalls of the upper electrode (110), wherein the spacer comprises a first upper surface (S1) arranged along a first side of the upper electrode and a second upper surface (S2) arranged along an opposing second side of the upper electrode, the first upper surface (S1) having a different width than the second upper surface (S2) [Fig. 1B, annotated below].
[AltContent: textbox (D)][AltContent: arrow][AltContent: textbox (P)][AltContent: textbox (P)][AltContent: textbox (S3)][AltContent: textbox (S2)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (S3)][AltContent: textbox (S1)][AltContent: arrow]
PNG
media_image1.png
496
646
media_image1.png
Greyscale
Regarding claim 2, Hsieh discloses wherein the spacer further comprises a third upper surface (S3) directly over the upper electrode (110) and vertically above the first upper surface (S1) and the second upper surface (S2) [Fig. 1B, annotated above].
Regarding claim 5, Hsieh discloses wherein the capacitor dielectric (108) and the lower electrode (106) have widths that are equal to a distance (D) between opposing outermost sidewalls of the spacer (114) [Fig. 1B].
Regarding claim 7, Hsieh discloses wherein the lower electrode (106) has a lower surface that is above a pedestal (P) formed by the lower dielectric structure (102b) [Fig. 1B, annotated above].
Regarding claim 9, Hsieh discloses a capacitor structure, comprising:
one or more lower interconnects (103a/103b, 105a/105b) disposed within a lower dielectric structure (102a/102b) over a substrate (101) [Fig. 1B];
a lower electrode (106) arranged along sidewalls (111) and an upper surface (102s) of the lower dielectric structure (102b) [Fig. 1B];
a capacitor dielectric (108) arranged along sidewalls and an upper surface of the lower electrode [Fig. 1B];
an upper electrode (110) arranged along sidewalls and an upper surface of the capacitor dielectric [Fig. 1B]; and
a spacer (S1/S2) arranged along opposing outermost sidewalls of the upper electrode (110), wherein the spacer (S1/S2) has different widths along different sides of the upper electrode [Fig. 1B, annotated above].
Regarding claim 10, Hsieh discloses wherein the spacer (S1/S2) has a bottommost surface on the capacitor dielectric (108) [Fig. 1B, annotated above].
Regarding claim 12, Hsieh discloses wherein the spacer (114) continuously extends from along the opposing outermost sidewalls of the upper electrode (110) to directly over (consider the spacer portion S3) the upper electrode (110) [Fig. 1B annotated above].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US 9620582) in view of Chuang et al. (US 9679909).
Regarding claim 8, Hsieh does not disclose the spacer continuously extends in a closed loop around an outermost perimeter of the upper electrode
However, Chuang teaches wherein the spacer (164/166) continuously extends in a closed loop around an outermost perimeter of the upper electrode (140) [Figs. 1A-1B].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Hsieh by including the spacer as taught by Chuang because it helps to reduce costs [col. 8, lines 4-7].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 9 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,154,939. Although the claims at issue are not identical, they are not patentably distinct from each other because they are not patentably distinct from each other because the instant claims are broader and therefore anticipated by the patent claims. For example,
In regard to claims 1 and 9, claim 9 of U.S. Patent No. 12,154,939 discloses a capacitor structure, comprising:
one or more lower interconnects disposed within a lower dielectric structure over a substrate [Claim 1];
a lower electrode arranged along sidewalls and an upper surface of the lower dielectric structure [Claim 1];
a capacitor dielectric [Claim 1]arranged along sidewalls and an upper surface of the lower electrode;
an upper electrode arranged along sidewalls and an upper surface of the capacitor dielectric [Claim 1]; and
a spacer arranged along outermost sidewalls of the upper electrode, wherein the spacer comprises a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode [Claim 1], the first upper surface having a different width than the second upper surface [Claim 9].
In regard to claims 2 and 12, claim 8 of U.S. Patent No. 12,154,939 discloses wherein the spacer further comprises a third upper surface directly over the upper electrode and vertically above the first upper surface and the second upper surface.
Claims 1, 7, 9-11 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,154,939 in view of Hsieh et al. (US 9620582).
In regard to claim 1 and 9, claim 1 of U.S. Patent No. 12,154,939 recites all the limitation except for the first upper surface having a different width than the second upper surface.
Hsieh teaches a spacer (114) arranged along outermost sidewalls of the upper electrode (110), wherein the spacer comprises a first upper surface (S1) arranged along a first side of the upper electrode and a second upper surface (S2) arranged along an opposing second side of the upper electrode, the first upper surface (S1) having a different width than the second upper surface (S2) [Fig. 1B, annotated above].
Regarding claim 7, Hsieh further teaches wherein the lower electrode (106) has a lower surface that is above a pedestal (P) formed by the lower dielectric structure (102b) [Fig. 1B, annotated above].
Regarding claim 10, Hsieh teaches wherein the spacer (S1/S2) has a bottommost surface on the capacitor dielectric (108) [Fig. 1B, annotated above].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify claim 1 of U.S. Patent No. 12,154,939 by including the spacer and pedestal as taught by Hsieh because it helps to protect the capacitor and improve performance [col. 2, lines 4-23].
Regarding claim 11, claim 4 of U.S. Patent No. 12,154,939 teaches a collective footprint that result in required 90%-95% coverage.
Regarding claim 14, claim 3 of U.S. Patent No. 12,154,939 teaches the recited first and second dielectric layers.
Allowable Subject Matter
Claims 3-6 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-20 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Jose R Diaz/Primary Examiner, Art Unit 2815
Prosecution Insights