DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This is response to application 18783574, a Divisional of U.S. application Ser. No. 17/825,225, filed on May 26, 2022,
This office action considers claims 1-14 and 21-26 pending for examination on merits.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (104; Fig 1; [0025] or C 3, L 16-39) = (element 102; Figure No. 1; Paragraph No. [0025]) or Column No 3, Line Nos. 16-39). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” or “Column No, Line Nos" shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference citation, in this case, Chen may not be preceded by the inventor tag, wherein the other reference citation. For example Wang, will carry inventor tag. These conventions are used throughout this document.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen; Hsiang-Fu et al. (US 20210061647 A) hereinafter Chen; in view of WANG; Zhi Dong (US 20190206739 A1) hereinafter Wang.
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Chen Figure 4. a representation of figs 1,2
Regarding Claim 1, Chen teaches an integrated chip (102, Fig 1; [0025]) comprising (see the entire document, Fig 1,4 along with relevant Figures and associated texts [0925+], and as cited below):
a semiconductor substrate (104; Figs 1-4; [0025]);
an interconnect structure (114; Figs 1-4; [0027]) overlying the semiconductor substrate;
an upper dielectric structure (124; [0027]) overlying the interconnect structure (114);
a microelectromechanical system (MEMS) substrate (136; [0033]) overlying the upper dielectric structure (124), wherein a cavity (148a of 148; [0059]) is defined between the MEMS substrate (136) and the upper dielectric structure (124), wherein the MEMS substrate (136) comprises a movable membrane (150a; [0039]) over the cavity (148a)
a cavity electrode (128a; [0029]) disposed in the upper dielectric structure (124) and underlying the cavity (148a);
a plurality of stopper structures (132) disposed in the cavity (148a) between the movable membrane (150a) and the cavity electrode(128a); and
a dielectric protection layer (212, 214) disposed along a top surface of the cavity electrode (128a).
But, Chen does not expressly disclose the dielectric protection layer has a greater dielectric constant than the upper dielectric structure.
However, in the analogous art, Wang discloses a semiconductor device ([0002]), wherein (Fig 9; [0081]) dielectric constant of protection layer 300 may be larger than the dielectric constant of the dielectric layer 230. The protection layer 300 may be made of high K materials e,g, of silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon oxyboronitride, or silicon oxyborocarbonitride materials.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the teaching of Wang into Cheng, and thereby, the combination of (Chen and Wang)’s IC comprises the dielectric protection layer (212, 214 in view of property of Wang) has a greater dielectric constant than the upper dielectric structure (124), since, at least, the protection layer 300 may improve the breakdown resistance and avoid the leakage between the electrode and the subsequent first plug, and may improve the breakdown resistance and avoid the leakage between the second electrode and the subsequent second plug (Wang [0082])
Regarding Claim 2, the combination of (Chen and Wang) as applied to the integrated chip of claim 1, further teaches, wherein (Figs 2-4,11) the dielectric protection layer (112) directly contacts the top surface of the cavity electrode ((128a;).
Regarding Claim 3, the combination of (Chen and Wang) as applied to the integrated chip of claim 1, further teaches, wherein the dielectric protection layer (112) comprises silicon nitride (Wang [0081]), silicon carbide, aluminum oxide, tantalum oxide, titanium oxide, zirconium oxide, or hafnium oxide.
Regarding Claim 4, the combination of (Chen and Wang) as applied to the integrated chip of claim 1, further teaches, wherein (Fig 1-4) the stopper structures (132) are part of the dielectric protection layer (because 130 comprises 132, 134 [0031]).
Regarding Claim 5, the combination of (Chen and Wang) as applied to the integrated chip of claim 1, further teaches, wherein the stopper structures are part of the upper dielectric structure and directly overlie protrusions extending from the dielectric protection layer (130 comprises 132, 134 [0031]).
Regarding Claim 6, the combination of (Chen and Wang) as applied to the integrated chip of claim 1, further teaches, wherein a thickness of the dielectric protection layer is less than a thickness of the cavity electrode (Fig 4).
Regarding Claim 7, the combination of (Chen and Wang) as applied to the integrated chip of claim 6, further teaches, wherein the dielectric protection layer (130 comprises 132, 134 ) directly contacts (Fig 4,11) opposing sidewalls of the cavity electrode (128a).
Regarding Claim 8, the combination of (Chen and Wang) as applied to the integrated chip of claim 1, further teaches, wherein a thickness of the dielectric protection layer is within a range of about 300 angstroms to 25,000 angstroms (obvious from Wang [0063]).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention
Claims 9-14 and 21-26 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Chen; Hsiang-Fu et al. (US 20210061647 A) hereinafter Chen.
Regarding Claim 9, Chen teaches an integrated chip (102, Fig 1, 4; [0025]) comprising (see the entire document, Fig 1,4 along with relevant Figures and associated texts [0925+], and as cited below):
a semiconductor substrate (104; Figs 1-4; [0025]);
an interconnect structure (114; Figs 1-4; [0027]) overlying the semiconductor substrate (104);
a lower dielectric structure (124; [0027]) overlying the semiconductor substrate (104);
a cavity electrode (128a; [0029]) disposed on the lower dielectric structure (124), wherein the cavity electrode (128a) comprises a stack of conductive layers (comprising {122,123, 128} as disclosed in [0027]);
an upper dielectric structure (132; [0031]) disposed over and around the cavity electrode (128a);
a cavity (148a of 148; [0059]) disposed in the upper dielectric structure (132) and overlying the cavity electrode (128a);
a microelectromechanical system (MEMS) substrate (136; [0033]) disposed on the upper dielectric structure (132), wherein the MEMS substrate (136) comprises a movable membrane (150a; [0039]) over the cavity (148a); and
a dielectric protection layer (130) disposed on and directly contacting a top surface of the cavity electrode (128a), wherein a thickness of the dielectric protection layer (130) is greater (because 130 comprises 132, 134 [0031]) than a thickness of the upper dielectric structure (132) directly over the cavity electrode (128a).
Regarding Claim 10, Chen as applied to the integrated chip of claim 9, further teaches, wherein the dielectric protection layer (130) comprises a high-k dielectric material (construed from [0031] a nitride (e.g., silicon nitride (SiN)), an oxy-nitride (e.g., silicon oxy-nitride (SiO.sub.XN.sub.Y)), some other dielectric material, or a combination of the foregoing).
Regarding Claim 11, Chen as applied to the integrated chip of claim 9, further teaches, wherein the thickness of the dielectric protection layer (130) is greater than (Fig 1; [0027]) a thickness of each individual conductive layer in the stack of conductive layers (of 128a).
Regarding Claim 12, Chen as applied to the integrated chip of claim 9, further teaches, wherein the stack of conductive layers (of 128a; [0027]) comprises a first conductive layer (122) on the lower dielectric structure, a second conductive layer (not labelled; Fig 1) on the first conductive layer (122) , a third conductive layer (123a) on the second conductive layer, and a fourth conductive layer (128a) on the third conductive layer (123a) , wherein (construed from [0027, 0030]) the first and third conductive layers comprise a first material and the second and fourth conductive layers comprise a second material different than the first material.
Regarding Claim 13, Chen as applied to the integrated chip of claim 9, further teaches, wherein outer opposing sidewalls of the dielectric protection layer (130) are aligned (depicted in Fig 1) with outer opposing sidewalls of the cavity electrode (128a).
Regarding Claim 14, Chen as applied to the integrated chip of claim 9, further teaches,, wherein the dielectric protection layer (130) comprises a plurality of stopper structures (214,216; Fig 4) extending upward from a lower surface of the dielectric protection layer, wherein the plurality of stopper structures abuts the cavity (148a) .
Regarding Claim 21, Chen teaches an integrated chip (102, Fig 1; [0025]) comprising (see the entire document, Fig 1,4 along with relevant Figures and associated texts [0925+], and as cited below):
an interconnect structure (114; Figs 1-4; [0027]) overlying a semiconductor substrate (104; Figs 1-4; [0025]);
a cavity electrode (128a; [0029]) overlying the interconnect structure (114);
an upper dielectric structure (124; [0027]) overlying the cavity electrode (128a);
a microelectromechanical system (MEMS) substrate (136; [0033]) overlying the upper dielectric structure (124), wherein a cavity (148a) is defined between the MEMS substrate (136) and the upper dielectric structure (124), wherein the MEMS substrate (136) comprises a movable element (150a; [0039]) over the cavity (128a) and the cavity electrode (128a); and
a dielectric protection layer (130) disposed along a top surface of the cavity electrode (128a), wherein the upper dielectric structure (124) comprises a first material ([0030]: comprise one or more stacked dielectric layers, which may respectively comprise a low-k dielectric (e.g., a dielectric material with a dielectric constant less than about 3.9), an oxide (e.g., silicon dioxide (SiO.sub.2)), or the like ) and the dielectric protection layer (130) comprises a second material ([0031] a nitride (e.g., silicon nitride (SiN)), an oxy-nitride (e.g., silicon oxy-nitride (SiO.sub.XN.sub.Y)), some other dielectric material, or a combination of the foregoing) different from the first material, wherein the upper dielectric structure (124) directly contacts outer opposing sidewalls of the dielectric protection layer (130) .
Regarding Claim 22, Chen as applied to the integrated chip of claim 21, further teaches, wherein outer opposing sidewalls of the dielectric protection layer (130) are aligned (depicted in Fig 1) with outer opposing sidewalls of the cavity electrode (128a).
Regarding Claim 23, Chen as applied to the integrated chip of claim 21, further teaches, wherein the cavity electrode (128a [0027]) comprises a plurality of conductive layers ({122,123,128a}) , wherein a thickness of the dielectric protection layer (130) is greater than an individual thickness of each conductive layer in the plurality of conductive layers, wherein the thickness of the dielectric protection layer (130) is less (construed from Fig 1,4) than an overall thickness of the cavity electrode ({122,123,128a}).
Regarding Claim 24, Chen as applied to the integrated chip of claim 21, further teaches, wherein the cavity electrode (128a [0027]) directly contacts (Fig 1) one or more conductive interconnect elements ({122,123,128a}) in the interconnect structure, wherein a height of the cavity electrode is greater (depicted in Fig 1) than a height of the one or more conductive interconnect elements.
Regarding Claim 25, Chen as applied to the integrated chip of claim 21, further teaches, wherein the upper dielectric structure (124; [0027]) continuously extends (depicted in Fig 4) along a top surface of the dielectric protection layer (130).
Regarding Claim 26, Chen as applied to the integrated chip of claim 21, further teaches, wherein a height of the dielectric protection layer (130) discretely changes (depicted in Fig 4) at least two times from a first sidewall in the outer opposing sidewalls in a direction towards a second sidewall in the outer opposing sidewalls.
Conclusion
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
September 26, 2026
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