DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the application filed on 7/25/24. Claims 2-21 are pending.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 7/25/24 and 5/16/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US PGPub 2019/0006487, hereinafter referred to as “Huang”, IDS reference).
Huang discloses the semiconductor device as claimed. See figures 1A-4 and corresponding text, where Huang teaches, in claim 2, a method comprising:
forming a first gate dielectric (118), a second gate dielectric, and a third gate dielectric over a first semiconductor region (120a), a second semiconductor region (122), and a third semiconductor region, respectively, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are in a first device region, a second device region, and a third device region, respectively;
depositing a first dopant-containing layer overlapping the first gate dielectric, the second gate dielectric, and the third gate dielectric, wherein the first dopant-containing layer comprises a first dopant; etching the first dopant-containing layer from the second device region, wherein the first dopant-containing layer comprises a remaining portion overlapping the first gate dielectric;
depositing a second dopant-containing layer comprising a second dopant in the first device region and the second device region; and
performing an anneal process to drive the first dopant and the second dopant in the first dopant-containing layer and the second dopant-containing layer into the first gate dielectric and the second gate dielectric, respectively, wherein during the anneal process, the third device region is free from the first dopant-containing layer and the second dopant-containing layer therein (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 3, wherein the first dopant is same as the second dopant (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 4, wherein the first dopant and the second dopant comprise lanthanum (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 5, further comprising forming a work-function layer over the first gate dielectric, wherein a peak atomic percentage of the first dopant and the second dopant is at an interface between the first gate dielectric and the work-function layer (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 6, wherein the first gate dielectric, the second gate dielectric, and the third gate dielectric comprise high-k dielectric layers extending on sidewalls and top surfaces of neighboring gate spacers (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 7, wherein when the anneal process is performed, the third gate dielectric is free from any dopant-containing layer that comprises at least one of the first dopant and the second dopant thereon (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 8, wherein when the anneal process is performed, a top surface of the third gate dielectric is revealed (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 9, further comprising, before the anneal process, removing both of the first dopant-containing layer and the second dopant-containing layer from the third device region (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 10, further comprising, before the anneal process, removing the first dopant-containing layer and the second dopant-containing layer from the third device region using a same etching mask (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 11, wherein a first portion of the second dopant-containing layer is in physical contact with the remaining portion of the first dopant-containing layer (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 12, further comprising:
after the anneal process, removing the first dopant-containing layer and the second dopant-containing layer (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 13, wherein the depositing the first dopant-containing layer comprises depositing an oxide layer that comprises the first dopant (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 14, a method comprising: (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073])
forming a first transistor comprising:
forming a first high-k dielectric over a first semiconductor region, wherein the first high-k dielectric comprises a first high-k dielectric material and lanthanum with a first lanthanum atomic percentage; and
forming a first work-function layer over the first high-k dielectric, wherein the lanthanum has a peak atomic percentage at an interface of the first high-k dielectric and the first work-function layer; and
forming a second transistor comprising: forming a second high-k dielectric over a second semiconductor region, wherein the second high-k dielectric comprises the first high-k dielectric material and lanthanum with a second lanthanum atomic percentage, and wherein the second lanthanum atomic percentage is lower than the first lanthanum atomic percentage; and
forming a second work-function layer over the second high-k dielectric.
Huang teaches, in claim 15, wherein the first transistor that comprises the lanthanum in the first high-k dielectric and the second transistor that comprises the lanthanum in the second high-k dielectric comprise an n-type transistor and a p-type transistor (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 16, wherein both of the first transistor that comprises the lanthanum in the first high-k dielectric and the second transistor that comprises the lanthanum in the second high-k dielectric are n-type transistors (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 17, wherein both of the first transistor that comprises the lanthanum in the first high-k dielectric and the second transistor that comprises the lanthanum in the second high-k dielectric are p-type transistors.
Huang teaches, in claim 18, wherein the forming the first high-k dielectric and the forming the second high-k dielectric comprise:forming a first lanthanum-containing layer over the first high-k dielectric; forming a second lanthanum-containing layer over the second high-k dielectric; and performing an anneal process, wherein the lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer are simultaneously driven into the first high-k dielectric and the second high-k dielectric, respectively (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 19, a method comprising: (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073])
forming a first source/drain region and a second source/drain region aside of a first semiconductor fin and a second semiconductor fin, respectively, wherein the first source/drain region and the second source/drain region are of opposite conductivity types; forming a first gate dielectric and a second gate dielectric on the first semiconductor fin and the second semiconductor fin, respectively;
depositing a first dopant-containing layer on both of the first gate dielectric and the second gate dielectric; etching the first dopant-containing layer, wherein after the etching, the first gate dielectric is covered by a first portion of the first dopant-containing layer, and the second gate dielectric is exposed;
depositing a second dopant-containing layer overlapping both of the first gate dielectric and the second gate dielectric; and performing an anneal process to drive dopants in the first dopant-containing layer and the second dopant-containing layer into the first gate dielectric and the second gate dielectric.
Huang teaches, in claim 20, wherein the dopants in the first dopant-containing layer and the second dopant-containing layer are same as each other (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Huang teaches, in claim 21, further comprising:
forming a first work-function layer over the first gate dielectric; and forming a second work-function layer over the second gate dielectric, wherein the first work-function layer and the second work-function layer are of opposite types (figures 1l and 1J and figures 1R-1T; [0034-0039], [0065-0073]).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 August 8, 2026
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