Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 33 and 41
b. Pending: 1-8 and 33-44
Claims 9-32 have been canceled without traverse and claims 33-44 have been newly added.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Election/Restrictions
Applicant’s election without traverse of claims 1-8 in the reply filed on 5/11/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) are submitted on 7/25/2024, 7/29/2024 and 1/29/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 and 33-44 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15-20 of U.S. Patent No. 12309990. Although the claims at issue are not identical, they are not patentably distinct from each other because when we combine all the limitations of claims 15-20 of USP’990, we find that they cover all the limitations of claims 1-8, 33-40 and 41-44 of Instant Application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 34 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
“the first memory element is coupled between the first output terminal and a first backup bit line”. It is unclear whether the phrase in bold letters mean the first output terminal of the first inverter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 33, 35-38 and 41-44 are rejected under 35 U.S.C. 103 as being unpatentable over Disney (US 20210005531) in view of Aritome (US 20070173018).
Regarding independent claim 1, Disney discloses an integrated circuit (Figs. 1-6), comprising:
a plurality of semiconductor devices disposed on a substrate (Figs. 3A-3B and [0033] describes semiconductor substrate 62 in and/or on which semiconductor devices are fabricated);
a dielectric structure overlying the semiconductor devices (Figs. 3A-3B and [0034] describes plurality dielectric layers 66 (1 through N) over substrate 62);
a plurality of conductive interconnect elements disposed within the dielectric structure and electrically coupled to one or more of the semiconductor devices (Figs. 3A-3B and [0034] describes various metal and dielectric layer deposition and etching processes may be performed according to conventional integrated circuit processing to form a plurality dielectric layers 66 (1 through N), each with an embedded metallization structure 68, in selective contact with electrodes of the driver device 60); and
a data backup unit overlying the plurality of conductive interconnect elements, wherein the data backup unit comprises a first source/drain structure, a second source/drain structure (Fig. 1 and [0027] describes two source/drain electrodes 24 and 25), a channel layer laterally extending over the first and second source/drain structures (Fig. 1 and [0027] describes channel along heterojunction 22), a first upper gate structure, and a second upper gate structure, wherein the first and second upper gate structures overlie the channel layer (Fig. 1 and [0028] describes gate structure 26 over channel).
Disney is silent about a data backup unit overlying the plurality of conductive interconnect elements, a first upper gate structure, and a second upper gate structure,
However, Aritome teaches a data backup unit overlying the plurality of conductive interconnect elements (Fig. 1 and [0021] describes memory cells are used to store data that are accessed via a data (DQ) link 124), a first upper gate structure, and a second upper gate structure (Fig. 4 and [0042] describes a channel region formed between the source 410 and drain 412, multiple control gates 416 are disposed within memory array 400).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Aritome to Disney in order to reduce the number of fabrication steps as taught by Aritome ([0007]-[0009]).
Regarding claim 2, Disney and Aritome together disclose all the elements of claim 1 as above and through Disney further the first and second source/drain structures are disposed on a bottom surface of the channel layer (Fig. 1 shows source/drain electrodes 24 and 25. That means source/drain region are underneath active layer 18), wherein the first and second upper gate structures are disposed on a top surface of the channel layer ((Fig. 1 shows gate 26 above active layer 18 and [0025] describes that layer 20 is optional and formed over the second active layer 18).
Regarding claim 4, Disney and Aritome together disclose all the elements of claim 1 as above and through Aritome further the data backup unit further comprises: a bottom gate structure disposed on a bottom surface of the channel layer, wherein the bottom gate structure is disposed laterally between the first and second source/drain structures (Figs. 3A-3B and 4 shows bottom gate structure 414 is disposed laterally between the first and second source/drain structures).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Aritome to modified Disney in order to reduce the number of fabrication steps as taught by Aritome ([0007]-[0009]).
Independent claim 33 recites the same limitations of independent claim 1 and henceforth rejected the same way along with additional limitation:
wherein a lower surface of the data backup unit is vertically offset from a top surface of the plurality of semiconductor devices by a first distance (Aritome in Figs. 1, 4 and corresponding sections of the Specification teaches data backup unit. For stacked memory devices, it is common practice to use vertical distance).
Regarding claim 35, Disney and Aritome together disclose all the elements of claim 33 as above and further the lower surface of the data backup unit is defined by a lower surface of the first source/drain structure (POSITA would define data backup unit in various ways).
Claim 36 recites the same limitations of claim 4 and henceforth rejected the same way.
Regarding claim 37, Disney and Aritome together disclose all the elements of claim 36 as above and through Aritome further a top surface of the lower gate structure is aligned with top surfaces of the first and second source/drain structures (Figs. 3A-3B shows that gate and source/drain structures are aligned).
Regarding claim 38, Disney and Aritome together disclose all the elements of claim 36 as above and through Aritome further the channel layer continuously vertically extends from a top surface of the lower gate structure to a bottom surface of the first upper gate structure (Fig. 4 shows there is vertical channel between the two gate structures).
Independent claim 41 recites the same limitations of independent claim 1 and henceforth rejected the same way along with additional limitation:
wherein a vertical distance between the first source/drain structure and the first upper gate structure is equal to a thickness of the channel layer (To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960)).
Regarding claim 42, Disney and Aritome together disclose all the elements of claim 41 as above and through Disney further the channel layer comprises a metal oxide (Fig. 1 and [0028] describes a metal-oxide-semiconductor gate structure 26 that likewise serves to modulate the conductivity of the channel at heterojunction 22).
Regarding claim 43, Disney and Aritome together disclose all the elements of claim 41 as above and through Disney further the first and second upper gate structures respectively comprise an upper gate electrode over a data storage layer (Fig. 5 and [0043] describes a gate electrode 26).
Regarding claim 44, Disney and Aritome together disclose all the elements of claim 41 as above and through Aritome further a bottom surface of the first upper gate structure is coplanar with a bottom surface of the second upper gate structure (Fig. 4 and [0042] describes a channel region formed between the source 410 and drain 412, multiple control gates 416 are disposed within memory array 400 and bottom surfaces are coplanar).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Aritome to modified Disney in order to reduce the number of fabrication steps as taught by Aritome ([0007]-[0009]).
Claims 7-8, 34 are rejected under 35 U.S.C. 103 as being unpatentable over Disney (US 20210005531) in view of Aritome (US 20070173018) and Lee (US 20140085978).
Regarding claim 7, Disney and Aritome together disclose all the elements of claim 1 as above and through Lee further the plurality of semiconductor devices comprises a first inverter coupled to a first access transistor at a first data storage node and a second inverter coupled to a second access transistor at a second data storage node, wherein the first source/drain structure is electrically coupled to the first data storage node and the second source/drain structure is electrically coupled to the second data storage node (Figs. 1A-1B and claim 21 recites a first inverter associated with a first data node and a second inverter associated with a second data node, the first data node and the second data node being coupled to a first word line and two complementary bit lines respectively via a first access transistor and a second access transistor).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to modified Disney in order to keep Flash old data and new updated data simultaneously before power-down period with a novel NVSRAM cell comprising one SRAM cell and at least two flash cells as taught by Lee ([0007]).
Regarding claim 8, Disney and Aritome together disclose all the elements of claim 1 as above and through Lee further the plurality of semiconductor devices are configured as a static random-access memory (SRAM) cell, and wherein the data backup unit is configured to store data of the SRAM cell in the first and second upper gate structures when power is removed from the SRAM cell ([0010]; 1) describes write operation performed from each SRAM cell into each corresponding Flash cell of each NVSRAM cell simultaneously and collectively upon the power loss cycle).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to modified Disney in order to keep Flash old data and new updated data simultaneously before power-down period with a novel NVSRAM cell comprising one SRAM cell and at least two flash cells as taught by Lee ([0007]).
Regarding claim 34, Disney and Aritome together disclose all the elements of claim 33 as above and through Lee further the plurality of semiconductor devices comprises a first inverter and a first pass-gate transistor coupled between a first output terminal of the first inverter and a first bit line, wherein the first upper gate structure is part of a first memory element of the data backup unit, wherein the first memory element is coupled between the first output terminal and a first backup bit line (Figs. 1A-1B show inverter INV1 and access transistor M1 coupled between output terminal of INV1 and bit line BL. Transistor and pass-gate transistor are interchangeable. Memory elements are coupled between bit lines BL and BLB).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to modified Disney in order to keep Flash old data and new updated data simultaneously before power-down period with a novel NVSRAM cell comprising one SRAM cell and at least two flash cells as taught by Lee ([0007]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 6/23/2026
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