Prosecution Insights
Last updated: August 17, 2026
Application No. 18/783,807

3DIC WITH GAP-FILL STRUCTURES AND THE METHOD OF MANUFACTURING THE SAME

Non-Final OA §102
Filed
Jul 25, 2024
Priority
Aug 21, 2023 — provisional 63/520,705 +1 more
Examiner
GEYER, SCOTT B
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
682 granted / 724 resolved
+34.2% vs TC avg
Minimal +4% lift
Without
With
+4.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
21 currently pending
Career history
733
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
21.5%
-18.5% vs TC avg
§102
40.8%
+0.8% vs TC avg
§112
24.3%
-15.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 724 resolved cases

Office Action

§102
DETAILED ACTION Information Disclosure Statement The references cited within the IDS documents have been considered. IDS document dates: July 25, 2024; August 29, 2024; November 12, 2024; December 20, 2024; June 4, 2025. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2021/0005595 A1, hereinafter referred to as ‘Chen’). As to claim 1, Chen teaches a structure (see figures 9-13) comprising: a bottom die (2/20); a top die over (44A or 44B) and bonding to the bottom die, wherein the top die comprises a top metal pad; a dielectric liner (54) comprising a vertical portion on sidewalls of the top die, and a horizontal portion on the bottom die; a gap-fill layer (56/58/60) overlapping the horizontal portion of the dielectric liner, wherein the gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon dioxide (gap-fill layer can be SiC, SiN, or SiON, see paragraphs 0033-0036); a through-via (70) penetrating through the dielectric liner and the gap-fill layer, wherein the through-via contacts the top metal pad; and a redistribution structure (see figures 10-13) over and electrically coupling to the top die and the through-via. As to claim 2, Chen teaches the gap-fill layer comprises an amorphous silicon-based dielectric material (i.e. SiOCN, see paragraphs 0033-0036). As to claim 4, Chen teaches the gap-fill layer comprises: a first sub layer comprising a first material; and a second sub layer over the first sub layer, wherein the second sub layer comprises a second material different from the first material. See figure 9, numerals 56, 58, and 60; see also see paragraphs 0033-0036). Allowable Subject Matter Claims 3, 5, and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. As to claim 3, the prior art of record does not teach or suggest the disclosed invention regarding wherein the gap-fill layer comprises a semiconductor material. As to claim 5, the prior art of record does not teach or suggest the disclosed invention regarding wherein a first one of the first sub layer and the second sub layer comprises a semiconductor, and a second one of the first sub layer and the second sub layer comprises a dielectric material. As to claim 6, the prior art of record does not teach or suggest the disclosed invention regarding wherein the through-via comprises a plurality of lateral protrusions. // Claims 7-20 are allowable. The following is an examiner’s statement of reasons for allowability. The prior art of record does not teach or suggest the disclosed invention regarding – A structure comprising: a first dielectric liner comprising a first portion on sidewalls of the top die, and a second portion on a top surface of the bottom die; a gap-fill layer contacting the first dielectric liner, wherein the gap-fill layer comprises a first sub layer comprising a semiconductor material; and a second dielectric liner encircling the through-via, wherein the second dielectric liner electrically insulates the through-via from the gap-fill layer, as recited within claim 7. A structure comprising: a gap-fill region between the first device die and the second device die, wherein the gap-fill region comprises a multi-layer stack comprising: a first plurality of layers comprising a first material; and a second plurality of layers comprising a second material different from the first material, wherein the first plurality of layers and the second plurality of layers are located alternatingly; and a through-via in the first plurality of layers and the second plurality of layers, as recited within claim 17. Claims 8-16 depend from claim 7; claims 18-20 depend from claim 17. Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in U.S.A. or Canada) or 571-272-1000. /SCOTT B GEYER/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jul 25, 2024
Application Filed
Aug 27, 2024
Response after Non-Final Action
Jul 20, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.3%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 724 resolved cases by this examiner. Grant probability derived from career allowance rate.

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