Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/25/2024 and 08/14/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1,5,7-8,10-11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chu et al, US 20210098405 A1.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
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Pertaining to claim 1, Chu teaches ( see fig.1 above) An integrated chip, comprising: a conductive feature [114]disposed over a dielectric structure[112] on a substrate[102] ; a first layer arranged[116] on peripheral regions of the conductive feature[114]; a second layer[118] having a bottommost surface arranged on the first layer[116], wherein the second layer [118] comprises a material that etches at a higher rate than the first layer when exposed to a first etchant and that etches at a lower rate than the first layer when exposed to a second etchant; and an additional conductive feature [120] extending through the first layer [116] and the second layer [118] to contact the conductive feature[114].
Pertaining to claim 5, Chu teaches ( see fig.1 above) The integrated chip of claim 1, wherein the conductive feature[114 or 114a] comprises a first metal ( see para 0026), the first layer[116] comprises a second metal ( see para0027) that is different than the first metal, and the second layer[116] comprises a dielectric material ( see para 0027).
Pertaining to claim 7, Chu teaches ( see fig.1 above) An integrated chip, comprising: a bond pad structure[114] comprising a first metal[114a] and being disposed over a conductive feature [114b] within a dielectric structure [112] over a substrate[102], the bond pad structure[114] including a central region that is recessed below a peripheral region surrounding the central region ( see fig1); a protective layer[116] arranged on the peripheral region of the bond pad structure[114] and comprising a second metal that is different than the first metal( see para (0026-0027)), wherein the protective layer [114] wraps around the central region and a part of the peripheral region of the bond pad structure in a closed loop; a patterning structure[118] over an upper surface of the protective layer[116]; and a conductive bonding structure[120] arranged between interior sidewalls of the protective layer[116] and the patterning structure[118].
Pertaining to claim 8, Chu teaches ( see fig.1 above) The integrated chip of claim 7, wherein the conductive bonding structure comprises a conductive bump[120], a conductive post, or an under bump metallurgy.
Pertaining to claim 10, Chu teaches ( see fig.1 above) The integrated chip of claim 7, wherein the protective layer has a thickness that is in a range of between approximately 100 Å and approximately 500 Å ( see para 0027)
Pertaining to claim 11, Chu teaches ( see fig.2) The integrated chip of claim 7, wherein the protective layer[116 comprises a curved sidewall profile that causes the protective layer to have a sidewall with a concave curvature ( see fig.2).
Allowable Subject Matter
Claims 14-20 allowed.
The following is an examiner's statement of reasons for allowance: The closest prior art of record of Chu et al, US 20210098405 A1 teaches the limitation of An integrated chip, comprising: a bond pad structure disposed over a top interconnect within an inter-level dielectric (ILD) structure over a substrate, wherein the bond pad structure comprises aluminum copper and has a central region that is recessed below peripheral regions surrounding the central region; a titanium nitride layer arranged on at least a part of the peripheral regions of the bond pad structure; a silicon oxynitride layer arranged on the titanium nitride layer, but it does not teach or suggest, singularly or in combination, at least the limitations of the independent claim 1 including “a undoped silicate glass layer disposed over the silicon oxynitride layer and along opposing outermost sidewalls of the bond pad structure; and a silicon nitride layer disposed over the undoped silicate glass layer.
Claims 2-4,6,9,12-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897
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