DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s continuity application filed on 07/25/2024.
Currently claims 1-20 are pending in the application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/25/2025 and 03/03/2026 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 10, 12, 15 and 17 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claims 10 and 17,
Claim 10 recites “further comprising turning parameters of the forming of the first ferroelectric layer and the forming of the second ferroelectric layer” (claim 10, lines 1–3), and claim 17 similarly recites “turning parameters of forming of the first FSL and of forming the second FSL” (claim 17, lines 1–2). The term “turning parameters” has no established meaning in the art in this context and renders the claim indefinite, as it is unclear what act is being performed. It appears from the specification that the applicant intended “tuning parameters” (i.e., adjusting process parameters). Because the metes and bounds of the recited act cannot be determined, the claims are indefinite. Clarification and/or correction is required. For purposes of examination, “turning parameters” is interpreted as “tuning parameters” consistent with the specification. In claim 17, the doubled recitation “of forming of the first FSL and of forming the second FSL” further compounds the ambiguity.
Regarding claims 12 and 15,
Claim 15 recites “wherein the forming of the transistor and the forming of the ferroelectric memory stack is configured to provides the transistor with a metal gate…” (claim 15, lines 1–3). This limitation is grammatically incongruent (“is” with a compound subject, and “configured to provides”), rendering the intended step indefinite. Further, claims 12 and 15 recite method steps using the apparatus-style functional phrase “configured to provide(s),” which renders it unclear whether a positive method step is being affirmatively required or merely a capability of the resulting structure. A person of ordinary skill in the art cannot determine the metes and bounds of the claimed method. Clarification and/or correction is required. For purposes of examination, the limitations are interpreted as affirmatively requiring the recited forming steps to yield the stated arrangement.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4 and 9 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2019/0066917 A1 (Nahar).
Regarding claim 1, Nahar discloses, a method comprising forming a ferroelectric stack of a memory device (a ferroelectric composite stack 14 for a ferroelectric capacitor / ferroelectric field-effect transistor memory cell; Figs. 2 and 11; [0004] – [0006], [0019] – [0020]) by:
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forming a first electrode (conductive material 30/48, a capacitor electrode, adjacent to the composite stack, which may be formed below the stack; Figs. 2 and 11; [0024], [0033], [0036]);
forming a first ferroelectric layer over the first electrode, where the first ferroelectric layer is formed of a first dielectric material (metal oxide-comprising insulator material 15; a hafnium- and zirconium-based oxide; Fig. 2; [0020]–[0021], [0025]).
forming a dielectric layer over the first ferroelectric layer, wherein the dielectric layer is formed of a second dielectric material, wherein the second dielectric material is different than the first dielectric material (non-ferroelectric insulating material 16 formed between and directly against the adjacent ferroelectric layers and of a composition different from that of its immediately-adjacent ferroelectric material (e.g., SiOx, Al2O3, TiOx); Fig. 2; [0020], [0022]).
forming a second ferroelectric layer over the dielectric layer, wherein the second ferroelectric layer is formed of the first dielectric material (metal oxide-comprising insulator material 17 (rendered ferroelectric), wherein all of the metal oxide-comprising insulator materials 15, 17, 19, 21 are formed to be of the same composition; Fig. 2; [0020], [0023]).
forming a second electrode over the second ferroelectric layer (conductive material 30 formed above the composite stack (and/or electrode 48); Figs. 2 and 11; [0024], [0033]).
wherein the forming of the first ferroelectric layer and the forming of the second ferroelectric layer provides the first dielectric material with a crystalline structure having orthorhombic crystalline phase (O-phase) portions and monoclinic crystalline phase (M-phase) portions, wherein a volume of the M-phase portions in the first dielectric material is less than about 10% (subjecting the stack to a temperature of at least 200 °C increases the quantity of orthorhombic crystalline phase in the metal oxide-comprising (ferroelectric) materials, and the interposed non-ferroelectric insulating materials 16, 18, 20 “function as non-ferroelectric crystallinity inhibitor materials that inhibit the formation of any non-ferroelectric phase in the composite stack” ([0025]–[0026]). The resulting film is rendered ferroelectric/crystalline — a material being “crystalline” if at least 90% by volume is crystalline ([0046]) — predominantly in the orthorhombic phase, such that the residual non-orthorhombic (monoclinic) portion is inherently less than about 10% ([0025]–[0026], [0046]).
Regarding claim 2, Nahar discloses, the method of claim 1, wherein the forming of the dielectric layer provides the second dielectric material with a non-crystalline structure (non-ferroelectric insulating material 16 has a non-crystalline structure — the non-ferroelectric insulating material comprises SiOx or insulative amorphous carbon and functions as a crystallinity-inhibitor; a material is “amorphous” if at least 90% by volume is amorphous; [0020], [0022], [0026], [0046]).
Regarding claim 4, Nahar discloses, the method of claim 1, wherein the first dielectric material (15) is a first metal oxide (hafnium/zirconium oxide-based ferroelectric material; [0021]) and the second dielectric material (16) is a second metal oxide (e.g., Al2O3/AlOx, TiOx, ZrOx; [0022]).
Regarding claim 9, Nahar discloses, the method of claim 1, wherein forming the first and second ferroelectric layers each with a thickness (10–100 Å) and the dielectric layer with a third thickness (1–30 Å), wherein the third (barrier) thickness is less than the first and second thicknesses ([0030]); Nahar further teaches that the metal oxide-comprising (ferroelectric) materials individually have a maximum thickness greater than the individual maximum thickness of each non-ferroelectric insulating material ([0020], [0030]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0066917 A1 (Nahar).
Regarding claim 8, Nahar discloses that the second dielectric (barrier) material comprises aluminum oxide (Al2O3/AlOx) while the ferroelectric material comprises a hafnium-oxide-based material ([0021]–[0022]). It would have been obvious that the second dielectric material has a first energy bandgap greater than the second energy bandgap of the first dielectric material, because aluminum oxide is well known to possess a larger energy bandgap than hafnium-oxide-based ferroelectric materials, and selecting a higher-bandgap barrier to reduce leakage current is a predictable use of a known material according to its established properties (MPEP 2143 (I) (B)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Nahar and MPEP 2143 (I) (B) before him/her, to modify the teachings of forming a ferroelectric stack of a memory device as taught by Nahar and make the second dielectric material having a first energy bandgap that is greater than a second energy bandgap of the first dielectric material.
Regarding claim 10, Nahar discloses, subjecting the composite stack to elevated temperature to increase the orthorhombic crystalline phase and to inhibit non-ferroelectric phase formation ([0025]–[0026]). It would have been obvious to tune the parameters of forming the first and second ferroelectric layers to provide the first dielectric material with a volume of M-phase portions of less than about 10%, since the amount of monoclinic phase is a result-effective variable that Nahar expressly seeks to minimize ([0025]–[0026], [0046]), and optimization thereof involves only routine skill (MPEP 2144.05 (II)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Nahar and MPEP 2144.05 (II) before him/her, to modify the teachings of forming a ferroelectric stack of a memory device as taught by Nahar and make the first and second ferroelectric layers to provide the first dielectric material with a volume of M-phase portions of less than about 10%.
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0066917 A1 (Nahar) and further in view of US 10,242,989 B2 (Pandey).
Regarding claim 18, Nahar discloses, a ferroelectric memory stack (a ferroelectric composite stack 14 for a ferroelectric capacitor / ferroelectric field-effect transistor memory cell; Figs. 2 and 11; [0004] – [0006], [0019] – [0020]) comprising a first electrode and a second electrode (conductive materials 30 and 48; [0024], [0033]),
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an FSL stack disposed between the first and second electrodes, the FSL stack including a first FSL (material 15), a second FSL (material 17), and a barrier layer (non-ferroelectric insulating material 16) disposed between the first and second FSLs, wherein the first and second FSLs are formed of a first dielectric material and the barrier layer is formed of a second, different dielectric material (Figs. 2 and 11; [0020]–[0023]), and
wherein the forming of the first ferroelectric layer and the forming of the second ferroelectric layer provides the first dielectric material with a crystalline structure having orthorhombic crystalline phase (O-phase) portions and monoclinic crystalline phase (M-phase) portions, wherein a volume of the M-phase portions in the first dielectric material is less than about 10% (subjecting the stack to a temperature of at least 200 °C increases the quantity of orthorhombic crystalline phase in the metal oxide-comprising (ferroelectric) materials, and the interposed non-ferroelectric insulating materials 16, 18, 20 “function as non-ferroelectric crystallinity inhibitor materials that inhibit the formation of any non-ferroelectric phase in the composite stack” ([0025]–[0026]). The resulting film is rendered ferroelectric/crystalline — a material being “crystalline” if at least 90% by volume is crystalline ([0046]) — predominantly in the orthorhombic phase, such that the residual non-orthorhombic (monoclinic) portion is inherently less than about 10% ([0025]–[0026], [0046]).
But Nahar does not expressly teach, forming a discrete transistor and a separate ferroelectric memory stack electrically connected by an interconnect structure.
However, in analogous art, Chavan discloses, a 1T-1C ferroelectric memory cell comprising an access transistor (source 504, drain 506, and gate electrode 560 over a gate dielectric 545) and a separate ferroelectric capacitor (bottom electrode 590, top electrode 595, and ferroelectric material 540 therebetween), wherein the capacitor is coupled to the drain 506 of the transistor by an interconnection structure 570 (a contact plug) (Fig. 5; col. 10, lines 43-67).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Nahar and Chavan before him/her, to arrange the ferroelectric composite-stack capacitor of Nahar as the ferroelectric memory stack of a 1T-1C cell electrically connected to a transistor by an interconnect structure as taught by Chavan, in order to form an addressable, individually programmable ferroelectric memory cell/array, since doing so merely combines prior-art elements according to known methods to yield predictable results (MPEP 2143 (I) (A)).
Regarding claim 20, Nahar discloses, the device of claim 18, wherein: the first dielectric material is hafnium oxide ([0021]) and the second dielectric material is aluminum oxide ([0022]).
Allowable Subject Matter
Claims 3, 5-7 and 19 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 3, the closest prior art, US 2019/0066917 A1 (Nahar), in conjunction with US 10,242,989 B2 (Pandey), and in combination with the other claimed features, fails to disclose, “the method of claim 1, wherein the forming of the first ferroelectric layer and the forming of the second ferroelectric layer provides the first dielectric material with a grain size of the M-phase portions that is less than about 3 nm”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the method of claim 1, wherein the forming of the first ferroelectric layer and the forming of the second ferroelectric layer provides the first dielectric material with a grain size of the M-phase portions that is less than about 3 nm,’ is material to the inventive concept of the application at hand to develop a ferroelectric non-volatile memory with excellent electrical properties, such as high speed read/write time, high switching endurance, and low power consumption.
Regarding claim 5, the closest prior art, US 2019/0066917 A1 (Nahar), in conjunction with US 10,242,989 B2 (Pandey), and in combination with the other claimed features, fails to disclose, “the method of claim 1, wherein the forming of the ferroelectric stack includes patterning the second electrode, the second ferroelectric layer, the dielectric layer, the first ferroelectric layer, and the first electrode to provide the ferroelectric stack with slanted sidewalls, such that the ferroelectric stack has a tapered width”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the method of claim 1, wherein the forming of the ferroelectric stack includes patterning the second electrode, the second ferroelectric layer, the dielectric layer, the first ferroelectric layer, and the first electrode to provide the ferroelectric stack with slanted sidewalls, such that the ferroelectric stack has a tapered width,’ is material to the inventive concept of the application at hand to develop a ferroelectric non-volatile memory with excellent electrical properties, such as high speed read/write time, high switching endurance, and low power consumption.
Regarding claim 6, the closest prior art, US 2019/0066917 A1 (Nahar), in conjunction with US 10,242,989 B2 (Pandey), and in combination with the other claimed features, fails to disclose, “the method of claim 1, wherein the forming of the ferroelectric stack includes patterning the second electrode, the second ferroelectric layer, the dielectric layer, the first ferroelectric layer, and the first electrode to provide the ferroelectric stack with vertical sidewalls, such that the ferroelectric stack has a uniform width”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the method of claim 1, wherein the forming of the ferroelectric stack includes patterning the second electrode, the second ferroelectric layer, the dielectric layer, the first ferroelectric layer, and the first electrode to provide the ferroelectric stack with vertical sidewalls, such that the ferroelectric stack has a uniform width,’ is material to the inventive concept of the application at hand to develop a ferroelectric non-volatile memory with excellent electrical properties, such as high speed read/write time, high switching endurance, and low power consumption.
Regarding claim 7, the closest prior art, US 2019/0066917 A1 (Nahar), in conjunction with US 10,242,989 B2 (Pandey), and in combination with the other claimed features, fails to disclose, “the method of claim 1, wherein the forming of the ferroelectric stack includes patterning the second electrode, the second ferroelectric layer, the dielectric layer, the first ferroelectric layer, and the first electrode to provide the ferroelectric stack with stepped sidewalls, such that the ferroelectric stack has a varying width”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the method of claim 1, wherein the forming of the ferroelectric stack includes patterning the second electrode, the second ferroelectric layer, the dielectric layer, the first ferroelectric layer, and the first electrode to provide the ferroelectric stack with stepped sidewalls, such that the ferroelectric stack has a varying width,’ is material to the inventive concept of the application at hand to develop a ferroelectric non-volatile memory with excellent electrical properties, such as high speed read/write time, high switching endurance, and low power consumption.
Regarding claim 19, the closest prior art, US 2019/0066917 A1 (Nahar), in conjunction with US 10,242,989 B2 (Pandey), and in combination with the other claimed features, fails to disclose, “the device of claim 18, wherein a grain size of the M-phase portions in the first dielectric material is less than about 3 nm”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the device of claim 18, wherein a grain size of the M-phase portions in the first dielectric material is less than about 3 nm,’ is material to the inventive concept of the application at hand to develop a ferroelectric non-volatile memory with excellent electrical properties, such as high speed read/write time, high switching endurance, and low power consumption.
Claims 11-17 are allowed.
Examiner’s Note: Claims 12, 15 and 17 have outstanding 112b rejections. Therefore, allowability of these claims depends on overcoming the 112b rejections.
The following is the examiner’s statement of reasons of allowance.
Independent claim 11 is allowable because the closest prior art US Patent Pub # US 2019/0066917 A1 to Nahar teaches,
a method comprising forming a ferroelectric stack (a ferroelectric composite stack 14 for a ferroelectric capacitor / ferroelectric field-effect transistor memory cell; Figs. 2 and 11; [0004] – [0006], [0019] – [0020]) by:
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forming a first electrode (Figs. 2 and 11; conductive material 30/48; [0024], [0033]),
forming a ferroelectric switching layer (FSL) stack over the first electrode (Figs. 2 and 11; composite stack 14 including a first FSL (material 15),
a second FSL (material 17), and
a barrier layer (non-ferroelectric insulating material 16) disposed between the first and second FSLs; [0020]),
wherein a first crystalline condition of the barrier layer differs from a second crystalline condition of the FSLs (the barrier being a non-ferroelectric crystallinity-inhibitor (amorphous) and the FSLs being rendered orthorhombic (with residual monoclinic); Figs. 2 and 11; [0022], [0025]–[0026], [0046]); and
forming a second electrode over the FSL stack (Figs. 2 and 11; [0024], [0033]).
forming a field-effect transistor having source/drain regions 44 and using the composite stack as the ferroelectric gate insulator (Figs. 2 and 11; [0033]–[0037]).
Furthermore, US Patent # US 10,242,989 B2 to Pandey discloses, a 1T-1C ferroelectric memory cell comprising an access transistor (source 504, drain 506, and gate electrode 560 over a gate dielectric 545) and a separate ferroelectric capacitor (bottom electrode 590, top electrode 595, and ferroelectric material 540 therebetween), wherein the capacitor is coupled to the drain 506 of the transistor by an interconnection structure 570 (a contact plug) (Fig. 5; col. 10, lines 43-67).
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However, neither Nahar nor any cited prior art, appear to explicitly disclose, in combination with the other claimed steps, the second crystalline condition is an orthorhombic phase and a monoclinic phase, and a grain size of monoclinic phase portions of the first FSL and the second FSL is less than about 3 nm;
Examiner’s Note: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by “the second crystalline condition is an orthorhombic phase and a monoclinic phase, and a grain size of monoclinic phase portions of the first FSL and the second FSL is less than about 3 nm”. Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, the claim is deemed patentable over the prior arts.
Specifically, the aforementioned ‘the second crystalline condition is an orthorhombic phase and a monoclinic phase, and a grain size of monoclinic phase portions of the first FSL and the second FSL is less than about 3 nm,’ is material to the inventive concept of the application at hand to develop a ferroelectric non-volatile memory with excellent electrical properties, such as high speed read/write time, high switching endurance, and low power consumption.
Dependent claims 12-17 depend, directly or indirectly, on allowable independent claim 11. Therefore, claims 12-17 are also allowable.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
1. US 2020/0251551 A1 (Okita) - A first-layer insulating film having a barrier property against a determined element contained in a ferroelectric capacitor as well as an oxygen permeability, a hydrogen permeability, and a water permeability is formed over a surface of the ferroelectric capacitor formed over a substrate. After that, heat treatment is performed in an oxidizing atmosphere. After the heat treatment, a second insulating film having a hydrogen permeability and a water permeability lower than those of the first-layer insulating film respectively is formed over a surface of the first-layer insulating film in a non-reducing atmosphere. A third-layer insulating film is formed over a surface of the second-layer insulating film. By doing so, degradation of a ferroelectric film under and after the formation of a semiconductor device having the ferroelectric capacitor is suppressed and deterioration in the characteristics of the ferroelectric capacitor is suppressed.
2. US 2020/0227423 A1 (Chavan) – A ferroelectric device includes a semiconductor material-containing region along a surface of the ferroelectric material nearest the electrode. The semiconductor material-containing region has a higher concentration of semiconductor material than a remainder of the ferroelectric material. The device may be, for example, a transistor or a capacitor. The device may be incorporated into a memory array. Some embodiments include a method of forming a ferroelectric capacitor. An oxide-containing ferroelectric material is formed over a first electrode. A second electrode is formed over the oxide-containing ferroelectric material. A semiconductor material-enriched portion of the oxide-containing ferroelectric material is formed adjacent the second electrode.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
07/21/2026
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