DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 7 recites the limitation "underlying conductive" in line 3. The meaning of the claim term is indefinite because the claim term is not used or defined in the specification.
For purpose of compact prosecution, “underlying conductive” will be treated as if it were “source/drain regions.”
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 4, 6, 15, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,569,362 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1-2, 4, 6, 15, and 20 are anticipated by claims 1-20 of the patent, and it is not patentably distinct from claims 1-20 of the patent. See the Table as shown below:
Under Examination Claims
Patented claims
1. A semiconductor device including a field effect transistor, comprising:
a source/drain region;
a first interlayer dielectric (ILD) layer disposed over the source/drain region;
a first contact disposed in the first ILD layer over the source/drain region;
a second contact disposed over the first contact;
an etch stop layer disposed over the first ILD layer; and
a second ILD layer disposed over the first ILD layer,
wherein: the first contact includes a first metal layer,
a silicide layer is formed on an upper surface of the first metal layer,
the second contact extends through the silicide layer,
a bottom surface of the second contact is in contact with the upper surface of the first metal layer,
the silicide layer includes a same metal element as the first metal layer, and
the etch stop layer covers an upper surface of the silicide layer.
Anticipated by Patented claims 1 and 7-8:
1. A semiconductor device including a field effect transistor, comprising:
a source/drain region;
a source/drain silicide layer formed on the source/drain region;
a first contact disposed in the interlayer dielectric layer over the source/drain silicide layer (as patented in claim 1);
7. A semiconductor device including a field effect transistor, comprising:
a first interlayer dielectric layer;
a first contact including a first metal layer, embedded in the first interlayer dielectric layer and disposed over an underlying conductive layer;
an adhesive layer disposed between the first contact and the underlying conductive layer;
a first silicide layer partially covering an upper surface of the first metal layer;
an insulating layer disposed over the first interlayer dielectric layer;
a second interlayer dielectric layer disposed over the insulating layer; and
a second contact embedded in the second interlayer dielectric layer and in contact with at least one of the silicide layer and the first contact,
wherein: the silicide layer is made of Co silicide and the first metal layer is made of Co, and
a bottom of the second contact is in contact with the first metal layer (note: the patented claim limitation of an insulating layer is equivalent to the claimed limitation of “etch stop layer”) (as patented in claim 7);
8. The semiconductor device of claim 7, wherein the bottom of the second contact is in contact with the upper surface of the first metal layer (as patented in claim 8).
2. The semiconductor device of claim 1, wherein: the first contact further includes an adhesive layer, and the adhesive layer is disposed between the first metal layer and the source/drain region.
Anticipated by Patented claim 2:
2. The semiconductor device of claim 1, wherein: the first contact further includes an adhesive layer, and the adhesive layer is disposed between the first metal layer and the source/drain silicide layer.
4. The semiconductor device of claim 1, wherein the silicide layer is made of cobalt silicide and the first metal layer is made of cobalt.
Anticipated by Patented claim 7:
7. A semiconductor device including a field effect transistor, comprising:
wherein: the silicide layer is made of Co silicide and the first metal layer is made of Co …
6. The semiconductor device of claim 1, wherein the etch stop layer is made of silicon nitride.
Anticipated by Patented claim 14:
14. The semiconductor device of claim 13, wherein the insulating layer includes at least one selected from the group consisting of SiN, SiC, SiCN and SiON.
15. A semiconductor device including a field effect transistor, comprising:
a first contact disposed over a conductive portion formed over a substrate and embedded in an interlayer dielectric layer, the first contact including a first metal layer and an adhesive layer disposed between the interlayer dielectric layer and the first metal layer; and
a second contact disposed over the first contact,
wherein: a silicide layer is formed on a portion of an upper surface of the first metal layer, and
a bottom of the second contact contacts the upper surface of the first metal layer.
Anticipated by Patented claims 7-8:
7. A semiconductor device including a field effect transistor, comprising:
a first interlayer dielectric layer;
a first contact including a first metal layer, embedded in the first interlayer dielectric layer and disposed over an underlying conductive layer;
an adhesive layer disposed between the first contact and the underlying conductive layer;
a first silicide layer partially covering an upper surface of the first metal layer;
an insulating layer disposed over the first interlayer dielectric layer;
a second interlayer dielectric layer disposed over the insulating layer; and
a second contact embedded in the second interlayer dielectric layer and in contact with at least one of the silicide layer and the first contact,
wherein: the silicide layer is made of Co silicide and the first metal layer is made of Co, and a bottom of the second contact is in contact with the first metal layer (as patented in patented claim 7);
8. The semiconductor device of claim 7, wherein the bottom of the second contact is in contact with the upper surface of the first metal layer (as patented in patented claim 8).
20. The semiconductor device of claim 15, wherein the silicide layer is made of Co silicide and the first metal layer is made of Co.
Anticipated by Patented claim 7:
7. A semiconductor device including a field effect transistor, comprising:
wherein: the silicide layer is made of Co silicide and the first metal layer is made of Co, and a bottom of the second contact is in contact with the first metal layer.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohara et al. (U.S. 2008/0233734 A1, hereinafter refer to Ohara).
Regarding Claim 1: Ohara discloses a semiconductor device including a field effect transistor (see Ohara, Figs.3E and 3L as shown below and ¶ [0012]), comprising:
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a source/drain region (13a) (see Ohara, Fig.3E as shown above);
a first interlayer dielectric (ILD) layer (23/30/31) disposed over the source/drain region (13a) (see Ohara, Fig.3E as shown above);
a first contact (24/25/40/41/43) disposed in the first ILD layer (23/30/31) over the source/drain region (13a) (see Ohara, Fig.3E as shown above);
a second contact (60/61/63) disposed over the first contact (24/25/40/41/43) (see Ohara, Figs.3E and 3L as shown above);
an etch stop layer (50) disposed over the first ILD layer (23/30/31) (see Ohara, Figs.3E and 3L as shown above); and
a second ILD layer (51/52/53) disposed over the first ILD layer (23/30/31) (see Ohara, Figs.3E and 3L as shown above),
wherein: the first contact (24/25/40/41/43) includes a first metal layer (43) (see Ohara, Fig.3E as shown above and ¶ [0086]),
a silicide layer (44) is formed on an upper surface of the first metal layer (43) (see Ohara, Figs.3E and 3L as shown above, Fig.3H, and ¶ [0049]- ¶ [0064]),
the second contact (60/61/63) extends through the silicide layer (44) (see Ohara, Fig.3L as shown above),
a bottom surface of the second contact (60/61/63) is in contact with the upper surface of the first metal layer (43) (see Ohara, Fig.3L as shown above),
the silicide layer (44) includes a same metal element (copper or tungsten) as the first metal layer (43) (see Ohara, Figs.3E and 3L as shown above, Fig.3H, ¶ [0049]- ¶ [0064], and ¶ [0086]), and
the etch stop layer (50) covers an upper surface of the silicide layer (44) (see Ohara, Figs.3E and 3L as shown above).
Regarding Claim 2: Ohara discloses a semiconductor device including a field effect transistor as set forth in claim 1 as above. Ohara further teaches wherein: the first contact (24/25/40/41/43) further includes an adhesive layer (25/40/41), and the adhesive layer (25/40/41) is disposed between the first metal layer (43) and the source/drain region (13a) (see Ohara, Fig.3E as shown above).
Regarding Claim 3: Ohara discloses a semiconductor device including a field effect transistor as set forth in claim 2 as above. Ohara further teaches wherein the silicide layer (44) contacts a side surface of the second contact (60/61/63) proximal to the bottom surface of the second contact (60/61/63) (see Ohara, Fig.3L as shown above).
Regarding Claim 5: Ohara discloses a semiconductor device including a field effect transistor as set forth in claim 1 as above. Ohara further teaches wherein the silicide layer (44) is made of tungsten silicide and the first metal layer (43) is made of tungsten (note: Ohara, demonstrated the first metal layer as formed from copper interconnect. Ohara further teaches tungsten material as alternative to copper material for forming the first metal layer 43, hence, ordinary skill in the art recognize that the tungsten material equally to be utilized for forming the first metal layer 43 and results that silicide layer to contain tungsten silicon material after plasma treatments) (see Ohara, Figs.3E and 3L as shown above, Fig.3H, ¶ [0049]- ¶ [0064], and ¶ [0086]).
Regarding Claim 6: Ohara discloses a semiconductor device including a field effect transistor as set forth in claim 1 as above. Ohara further teaches wherein the etch stop layer (50) is made of silicon nitride (see Ohara, Figs.3E and 3L as shown above and ¶ [0065]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7-17 and 19- 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (U.S. 2016/0126135 A1, hereinafter refer to Zhang) in view of Ohara et al. (U.S. 2008/0233734 A1, hereinafter refer to Ohara).
Regarding Claim 7: Zhang discloses a semiconductor device including a field effect transistor (see Zhang, Figs.1E and 3E as shown below and ¶ [0002]), comprising:
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a first interlayer dielectric (ILD) layer (24) (see Zhang, Figs.1E and 3E as shown above);
a first contact (28/32/102) disposed over an underlying conductive layer (22), wherein the first contact (28/32/102) includes a first metal layer (32/102) embedded in the first ILD layer (24) and an adhesive layer (28) disposed between the first metal layer (32/102) and the underlying conductive layer (22) (see Zhang, Figs.1E and 3E as shown above);
a first silicide layer (124) formed on an upper surface of the first metal layer (32/102) (see Zhang, Figs.1E and 3E as shown above);
an insulating layer (40) disposed over the first ILD layer (24) (see Zhang, Figs.1E and 3E as shown above);
a second ILD layer (42) disposed over the insulating layer (40) (see Zhang, Figs.1E and 3E as shown above); and
a second contact (110/112) embedded in the second ILD layer (42) (see Zhang, Figs.1E and 3E as shown above),
wherein: the silicide layer (124) is made of cobalt silicide and the first metal layer (32/102) is made of cobalt (see Zhang, Figs.1E and 3E as shown above, ¶ [0009], and ¶ [0034]).
Zhang is silent upon explicitly disclosing wherein the second contact extends through an opening in the silicide layer and contacts an upper surface of the first contact,
the insulating layer covers an upper surface of the silicide layer.
For support see Ohara, which teaches wherein the second contact (60/61/63) extends through an opening in the silicide layer (44) and contacts an upper surface of the first contact (40/41/43) (see Ohara, Fig.3L as shown above, Fig.3H, ¶ [0049]- ¶ [0064], and ¶ [0108]- ¶ [0109]),
the insulating layer (50) covers an upper surface of the silicide layer (44) (see Ohara, Fig.3L as shown above, Fig.3H, and ¶ [0108]- ¶ [0109]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhang and Ohara to enable the second contact of Zhang to extend through an opening in the silicide layer and contacts an upper surface of the first contact, and the insulating layer of Zhang to cover an upper surface of the silicide layer as taught by Ohara in order to improve electrical reliability of the semiconductor device.
Regarding Claim 8: Zhang as modified teaches a semiconductor device including a field effect transistor as set forth in claim 7 as above. The combination of Zhang and Ohara further teaches wherein the first silicide layer (44) contacts a side surface of the second contact (60/61/63) (see Ohara, Fig.3L as shown above).
Regarding Claim 9: Zhang as modified teaches a semiconductor device including a field effect transistor as set forth in claim 7 as above. The combination of Zhang and Ohara further teaches wherein the first silicide layer (44) contacts opposite side surfaces of the second contact (60/61/63) (see Ohara, Fig.3L as shown above).
Regarding Claim 10: Zhang as modified teaches a semiconductor device including a field effect transistor as set forth in claim 7 as above. The combination of Zhang and Ohara further teaches wherein the underlying conductive layer (13) comprises a second silicide layer (not shown) (see Ohara, Figs.3E and 3L as shown above and ¶ [0027]).
Regarding Claim 11: Zhang as modified teaches a semiconductor device including a field effect transistor as set forth in claim 10 as above. The combination of Zhang and Ohara further teaches wherein the second silicide layer (not shown) includes one or more of cobalt silicide, titanium silicide, nickel silicide, copper silicide, tungsten silicide, and molybdenum silicide (see Ohara, Figs.3E and 3L as shown above and ¶ [0027]).
Regarding Claim 12: Zhang as modified teaches a semiconductor device including a field effect transistor as set forth in claim 8 as above. The combination of Zhang and Ohara further teaches wherein a side of the first silicide (124) is in contact with the adhesive layer (28) (see Zhang, Fig.3E as shown above).
Regarding Claim 13: Zhang as modified teaches a semiconductor device including a field effect transistor as set forth in claim 8 as above. The combination of Zhang and Ohara further teaches wherein the insulating layer (40) is made of a different material than the first and second ILD layers (24/42) (see Zhang, Fig.3E as shown above).
Regarding Claim 14: Zhang as modified teaches a semiconductor device including a field effect transistor as set forth in claim 13 as above. The combination of Zhang and Ohara further teaches wherein the insulating layer (50) includes at least one selected from the group consisting of SiN, SiC, SiCN and SiON (see Ohara, Figs.3E and 3L as shown above and ¶ [0065]).
Regarding Claim 15: Zhang discloses a semiconductor device including a field effect transistor (see Zhang, Figs.1E and 3E as shown above and ¶ [0002]), comprising:
a first contact (28/32/102) disposed over a conductive portion (22) formed over a substrate (12) and embedded in an interlayer dielectric layer (24), the first contact (28/32/102) including a first metal layer (32/102) and an adhesive layer (28) disposed between the interlayer dielectric layer (24) and the first metal layer (32/102) (see Zhang, Figs.1E and 3E as shown above); and
a second contact (110/112) disposed over the first contact (28/32/102) (see Zhang, Fig.3E as shown above),
wherein: a silicide layer (124) is formed on a portion of an upper surface of the first metal layer (32/102) (see Zhang, Fig.3E as shown above).
Zhang is silent upon explicitly disclosing wherein a bottom of the second contact contacts the upper surface of the first metal layer.
For support see Ohara, which teaches wherein a bottom of the second contact contacts (60/61/63) the upper surface of the first metal layer (43) (see Ohara, Fig.3L as shown above, Fig.3H, ¶ [0049]- ¶ [0064], and ¶ [0108]- ¶ [0109]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhang and Ohara to enable the bottom of the second contact of Zhang to contact the upper surface of the first metal layer as taught by Ohara in order to improve electrical reliability of the semiconductor device.
Regarding Claim 16: Zhang as modified teaches a semiconductor device including a field effect transistor as set forth in claim 15 as above. The combination of Zhang and Ohara further teaches wherein an insulating layer (50) covers an upper surface of the silicide layer (44) (see Ohara, Fig.3L as shown above).
Regarding Claim 17: Zhang as modified teaches a semiconductor device including a field effect transistor as set forth in claim 16 as above. The combination of Zhang and Ohara further teaches wherein the second contact (60/61/63) has a tapered shape (see Ohara, Fig.3L as shown above).
Note: the configuration of the claimed second contact was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed second contact was significant
Regarding Claim 19: Zhang as modified teaches a semiconductor device including a field effect transistor as set forth in claim 15 as above. The combination of Zhang and Ohara further teaches wherein the adhesive layer (40/41) is in contact with a side of the silicide layer (44) (see Ohara, Fig.3L as shown above).
Regarding Claim 20: Zhang as modified teaches a semiconductor device including a field effect transistor as set forth in claim 15 as above. The combination of Zhang and Ohara further teaches wherein the silicide layer (124) is made of Co silicide and the first metal layer (32/102) is made of Co (see Zhang, Figs.1E and 3E as shown above, ¶ [0009], and ¶ [0034]).
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ohara et al. (U.S. 2008/0233734 A1, hereinafter refer to Ohara) as applied to claim 1 above, and further in view of Zhang et al. (U.S. 2016/0126135 A1, hereinafter refer to Zhang).
Regarding Claim 4: Ohara discloses a semiconductor device including a field effect transistor as applied to claim 1 above. Ohara is silent upon explicitly disclosing wherein the silicide layer is made of cobalt silicide and the first metal layer is made of cobalt.
For support see Zhang, which teaches wherein the silicide layer (124) is made of cobalt silicide and the first metal layer (32/102) is made of cobalt (see Zhang, Figs.1E and 3E as shown above, ¶ [0009], ¶ [0014], and ¶ [0034]).
Ohara discloses the claimed invention except for the material of first metal layer and silicide layer. Hence, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Ohara and Zhang to enable the known cobalt material for forming the first metal layer and the silicide layer of Ohara as taught by Zhang in order to improve interface between a conductive via and a conductive contact structure, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (U.S. 2016/0126135 A1, hereinafter refer to Zhang) and Ohara et al. (U.S. 2008/0233734 A1, hereinafter refer to Ohara) as applied to claim 15 above, and further in view of Liu et al. (U.S. 2004/0048468 A1, hereinafter refer to Liu).
Regarding Claim 18: Zhang as modified teaches a semiconductor device including a field effect transistor as applied to claim 15 above. The combination of Zhang and Ohara is silent upon explicitly disclosing wherein the adhesive layer includes a TiN layer formed on a Ti layer.
For support see Liu, which teaches wherein the adhesive layer (15) includes a TiN layer formed on a Ti layer (see Liu, Fig.1, ¶ [0007] and ¶ [0034]- ¶ [0035]).
The combination of Zhang and Ohara teaches the claimed invention except for the material of adhesive layer. Hence, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhang, Ohara, and Liu to enable the known adhesive layer includes a TiN layer formed on a Ti layer as taught by Liu in order to prevent first metal diffusion into the interlayer dielectric (ILD) layer, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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