DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/23/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement filed 7/25/2024 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because no copies of several references are present. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 8, 10-12, and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsui et al. (US Patent No. 6,060,344).
Regarding claim 1, Matsui discloses a substrate, comprising an electrically insulating layer (4) interposed between a single-crystal active layer (1) and a base substrate (6), the electrically insulating layer (4) having a first portion (2) with a first thickness and interposed between a polycrystalline layer (5) on the base substrate (6) and the active layer (1), and a second portion (3) with a second thickness greater than the first thickness, the second portion (3) interposed between the base substrate (6) and the active layer (1) adjacent the first portion (Figure 2G).
Regarding claim 2, Matsui discloses an additional layer (8) comprising polycrystalline silicon, the additional layer (8) interposed between the base substrate (6) and an assembly formed by active layer (1), the electrically insulating layer (4), and the polycrystalline layer (5) (Figure 2H).
Regarding claim 4, Matsui discloses the base substrate (6) comprises an epitaxially grown and doped layer adjacent the electrically insulating layer (col. 12, lines 55-69).
Regarding claim 8, Matsui discloses the thickness of the active layer (1) is not uniform (Figure 1).
Regarding claim 10, Matsui discloses at least a portion of the polycrystalline layer (5) is configured to function as a charge trapping layer (3) (There is nothing in the claims to differentiate the polycrystalline layer from the prior art, and therefore it would inherently function as a charge trapping layer).
Regarding claim 11, Matsui discloses at least a portion of the polycrystalline layer (5) is configured to function as a conductive layer (5) (There is nothing in the claims to differentiate the polycrystalline layer from the prior art, and therefore it would inherently function as a conductive layer).
Regarding claim 12, Matsui discloses at least a first portion (3) of the polycrystalline silicon layer (5) is configured to function as a charge trapping layer, and at least a second portion (5) of the polycrystalline layer (5) is configured to function as a conductive layer (There is nothing in the claims to differentiate the polycrystalline layer from the prior art, and therefore it would inherently function as a charge trapping layer and there is nothing in the claims to differentiate the polycrystalline layer from the prior art, and therefore it would inherently function as a conductive layer).
Regarding claim 15, Matsui discloses the active layer (1) comprises an epitaxial layer (col. 12, lines 55-69).
Regarding claim 16, Matsui discloses the active layer (1) comprises silicon or silicon-germanium (col. 12, lines 55-61).
Regarding claim 17, Matsui discloses the electrically insulating layer (4) comprises silicon oxide (col. 7, lines 3-10).
Regarding claim 18, Matsui discloses the polycrystalline layer (5) comprises silicon (col. 7, lines 25-30).
Regarding claim 19, Matsui discloses the electrically insulating layer (4) comprises silicon oxide (col. 7, lines 3-10).
Regarding claim 20, Matsui discloses the active layer (1) comprises silicon or silicon-germanium (col. 12, lines 55-61).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US Patent No. 6,060,344).
Regarding claim 7, Matsui discloses the limitations as discussed in the rejection of claim 1 above. Matsui does not disclose a thickness of the active layer is between 5 nm and 500 nm. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the thickness of the active layer to be within this range to minimize overall device size thereby improving device speed and efficiency, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 9, Matsui discloses the limitations as discussed in the rejection of claim 1 above. Matsui does not disclose each of the first thickness in the first portion of the electrically insulating layer and the second thickness in the second portion of the electrically insulating layer is between 10 nm and 500 nm. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the thickness of the insulating layer to be within this range to minimize overall device size thereby improving device speed and efficiency, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 3 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US Patent No. 6,060,344) in view of Schwarzenbach et al. (US Publication No. 2019/0348462).
Regarding claim 3, Matsui discloses the limitations as discussed in the rejection of claim 2 above. Matsui does not disclose an additional electrically insulating layer interposed between the additional layer and the base substrate. However, Schwarzenbach discloses multiple insulating layers (21/22/23) between a substrate (1) and an active layer (3). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date to have modified the insulating layer of Matsui to include an additional insulating layer, as taught by Schwarzenbach, since it can prevent electrical defects by avoiding recombinations between the active layer and metal layers (paragraph 115).
Regarding claim 14, Schwarzenbach discloses a sacrificial layer on the active layer, the sacrificial layer comprising a material capable of being selectively etched relative to the active layer (paragraph 128).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US Patent No. 6,060,344) in view of Hong et al. (US Publication No. 2013/0288058).
Regarding claim 5, Matsui discloses the limitations as discussed in the rejection of claim 4 above. Matsui does not disclose the base substrate comprises an integrated circuit. However, Hong discloses a base substrate that comprises an integrated circuit (paragraph 35). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the substrate of Matsui to include an integrated circuit, as taught by Hong, since it can improve the versatility of the device for a variety of applications by including arrays of devices including integrated circuits (paragraph 35).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US Patent No. 6,060,344) in view of Zhu et al. (US Patent No. 10,109,638).
Regarding claim 13, Matsui discloses the limitations as discussed in the rejection of claim 1 above. Matsu does not disclose at least one fully depleted silicon on insulator (FDSOI) device on the active layer over the first portion of the electrically insulating layer having the first thickness, and at least one radiofrequency (RF) device on the active layer over the second portion of the electrically insulating layer having the second thickness. However, Zhu discloses a FDSOI and RF device on an active layer with different thicknesses (Figure 4D). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the substrate of Matsui to include these devices on the active layer, as taught by Zhu, since the height difference allows coplanar top surfaces and the hybrid region enables disposing of transistors which suffer from floating body effects (abstract).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dumond et al. (US Publication No. 2013/0011626) discloses laminating a structure (6a) with an imprint pattern (10a) that has a second thickness greater than a first (Figure 1). Keil et al. (US Publication No. 2010/0155988) discloses an insulating layer having multiple thicknesses on a base substrate (Figure 2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/N.R.P/ 8/25/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights