Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/25/2024 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3,6,9 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,3-4,5,7,10 of U.S. Patent No. US 11756907 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the claims in U.S. Patent No. US 11756907 B2 teaches the scope of the claim limitations of application 18/784,164 being examined.
Attached here is a table of the claims rejected under double patenting by the claims of the parent case below.
Claim numbering that are anticipated
Instant Application Claims
Conflicting Application/Patent Claims by Chen (US 11756907 B2)
1
1. A package, comprising: a first component structure comprising: a first substrate; a first interconnect structure over the first substrate, the first interconnect structure having a first conductive pad; a first dielectric layer over the first interconnect structure; a first encapsulant along sidewalls of the first substrate, the first interconnect structure, and the first dielectric layer; a first bond pad via extending through the first dielectric layer to the first conductive pad; a first bonding layer over the first encapsulant and the first dielectric layer; and a first bond pad in the first bonding layer and on the first bonding pad via, wherein the first bond pad comprises a barrier layer and a metal fill, wherein a barrier layer extends between the metal fill and the first bond pad via, wherein a bottom surface the barrier layer is flat; and a second component structure bonded to the first component structure, the second component structure comprises: a second substrate; a second bonding layer on a first side of the second substrate; and a second bond pad in the second bonding layer, wherein the second bond pad is directly bonded to the first bond pad.
1. A device comprising: an interconnect structure over a first semiconductor substrate, the interconnect structure comprising a plurality of first conductive pads; a first dielectric layer over the interconnect structure; a plurality of bond pad vias within the first dielectric layer, wherein the plurality of bond pad vias couple to corresponding ones of the plurality of first conductive pads; a first bonding layer over the first dielectric layer; a conductive pad in the first dielectric layer, wherein the first dielectric layer separates the conductive pad and the first bonding layer; and a plurality of first bond pads within the first bonding layer, each first bond pad of the plurality of first bond pads comprising: a first barrier layer extending along sidewalls of the first bonding layer and on the plurality of bond pad vias; and a first conductive material over the first barrier layer, wherein the first barrier layer extends between corresponding ones of the plurality of bond pad vias and the first conductive material.
3. The device of claim 1, further comprising a first molding compound adjacent the first semiconductor substrate, the interconnect structure, and the first dielectric layer.
4. The device of claim 3, further comprising a die structure, the die structure comprising: a second semiconductor substrate; a second bonding layer; and a plurality of second bond pads bonded directly to corresponding ones of the plurality of first bond pads.
2
2. The package of claim 1, wherein the first dielectric layer extends along sidewalls of the first conductive pad.
1… a conductive pad in the first dielectric layer…
3
3. The package of claim 1, further comprising a second encapsulant along sidewalls of the second substrate and the second bonding layer.
5. The device of claim 4, further comprising a second molding compound along sidewalls of the second semiconductor substrate and the second bonding layer.
4
6. The package of claim 5, wherein the first component structure comprises a third bond pad in the first bonding layer, wherein the second component structure comprises a through via extending through the second encapsulant, wherein the through via directly contacts the third bond pad
7. The device of claim 5, further comprising a through via extending through the second molding compound to one of the plurality of first bond pads.
5
9. A package, comprising: a first component structure comprising: a first metallization layer, the first metallization layer comprising a plurality of metal pads; a first dielectric layer over the first metallization layer; a first bond pad via and a second bond pad via in the first dielectric layer on the first metallization layer, wherein an entirety of an upper surface of the first bond pad via and an upper surface of the second bond pad via are level with an upper surface of the first dielectric layer in a cross-sectional view; and a first bond pad on the first bond pad via and a second bond pad on the second bond pad via, wherein a first barrier layer extends between the first bond pad via and the first bond pad, wherein a bottom surface of the first barrier layer directly contacts the first dielectric layer and the first bond pad via; and a substrate comprising a third bond pad, wherein the third bond pad is directly bonded to the first bond pad.
10. A device, comprising: a first die structure comprising: a first metallization layer, the first metallization layer comprising a plurality of metal pads; a first dielectric layer over the first metallization layer; one or more first bond pad vias in the first dielectric layer on the first metallization layer, wherein an upper surface of the one or more first bond pad vias is level with an upper surface of the first dielectric layer; and one or more first bond pads on the one or more first bond pad vias, wherein a first barrier layer extends between each respective first bond pad via and a respective first bond pad, wherein a bottom surface of each first barrier layer is flat; and a substrate comprising one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die structure.
Allowable Subject Matter
Claims 16-20 allowed.
The following is an examiner's statement of reasons for allowance: The closest prior art of record of Wu (US 20210028148 A1) or Yu et al, ( 20190096817 A1) teaches the limitation of " A package, comprising: a first component structure comprising: a first dielectric layer, but it does not teach or suggest, singularly or in combination, at least the limitations of the independent claim 16 including “a first bond pad via extending through the first dielectric layer, an upper surface of the first bond pad via being level with an upper surface of the first dielectric layer; a first bonding layer over the first dielectric layer; and a first bond pad in the first bonding layer and on the first bonding pad via, wherein the first bond pad comprises a barrier layer and a metal fill, wherein a barrier layer extends between the metal fill and the first bond pad via, wherein a bottom surface the barrier layer is completely above the upper surface of the first dielectric layer; and a second component structure bonded to the first component structure, the second component structure comprises: a second substrate; a second bonding layer on a first side of the second substrate; and a second bond pad in the second bonding layer, wherein the second bond pad is directly bonded to the first bond pad.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897
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