Prosecution Insights
Last updated: October 22, 2026
Application No. 18/784,190

PERFORMING ANNEALING PROCESS TO IMPROVE FIN QUALITY OF A FINFET SEMICONDUCTOR

Non-Final OA §102§103
Filed
Jul 25, 2024
Priority
Jun 27, 2018 — provisional 62/690,614 +2 more
Examiner
TRAN, TONY
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
70%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
621 granted / 884 resolved
+2.2% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
49 currently pending
Career history
937
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
60.5%
+20.5% vs TC avg
§102
33.3%
-6.7% vs TC avg
§112
3.7%
-36.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 884 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-8, 12-15 and 18-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by BAO (Pub. No.: US 2018/0315663). Re claim 1, Bao teaches a method, comprising: providing a semiconductor device having an active region that protrudes vertically out of a substrate, wherein the active region contains germanium oxide ([5a/5b]/20a, FIG. 3, [0055]/[0056]); forming a capping layer (30/20a, FIG. 3 → 4) that wraps around the active region; reducing a content of the germanium oxide in the active region (by annealing to form 30, [0044]); and forming a dielectric layer (35/20b, [0056]) over the active region after the content of the germanium oxide has been reduced in the active region. Re claim 2, Bao teaches the method of claim 1, wherein the forming the capping layer comprises epitaxially growing [0028] the capping layer (30/20a) on the active region. Re claim 3, Bao teaches the method of claim 1, wherein the capping layer has a semiconductor material composition (30/20a). Re claim 4, Bao teaches the method of claim 1, wherein the germanium oxide is located at an interface (20a) between the active region ([5a/5b]/20a, FIG. 3) and the capping layer (30/20a of FIG. 4) after the capping layer has been formed. Re claim 5, Bao teaches the method of claim 1, wherein the reducing is performed at least in part by breaking a bond between a germanium element and an oxygen element of the germanium oxide ([5a/5b]/20a, FIG. 3) and allowing the germanium element and the oxygen element to diffuse outwards (30/20a of FIG. 4). Re claim 6, Bao teaches the method of claim 5, wherein: the oxygen element oxidizes at least a portion of the capping layer (to produce Silicon rich surface layer 30, [0046]); and the germanium element escapes the semiconductor device as a gaseous product [0045]. Re claim 7, Bao teaches the method of claim 1, wherein the reducing comprises performing an annealing process [0048]. Re claim 8, Bao teaches the method of claim 7, wherein the annealing process is performed with an energy level that causes atoms on a surface of the active region to rearrange themselves ([0048], FIG. 4). Re claim 12, Bao teaches the method of claim 1, wherein the capping layer (30/20a of FIG. 4) is thickened after the content of the germanium oxide has been reduced (20a). Re claim 13, Bao teaches the method of claim 1, wherein the dielectric layer is a part of a gate structure [0053]. Re claim 14, Bao teaches a method, comprising: trimming an active region of a semiconductor device, the active region (5a/5b of FIG. 2) protruding vertically out of a substrate; epitaxially growing [0018] a semiconductor layer on an upper surface and side surfaces of the active region, wherein a germanium oxide material (30/20a) is formed an interface between the active region and the semiconductor layer (20a); performing an annealing process to the semiconductor device, wherein process parameters of the annealing process are configured to break bonds between a germanium element and an oxygen element of the germanium oxide material ([0048], FIG. 4); and forming a dielectric layer (35/20b) over the active region after the annealing process has been performed. Re claim 15, Bao teaches the method of claim 14, wherein: the semiconductor layer contains silicon (20a); and the annealing process thickens the semiconductor layer (20a → 20a/30). Re claim 18, Bao teaches a method, comprising: trimming an active region of a semiconductor device, the active region (protruding vertically out of a substrate, wherein the active region (5a/5b of FIG. 2) has a first surface topography variation after the trimming; forming a semiconductor capping layer (20a, FIG. 3) that wraps around an upper surface and side surfaces of the active region; annealing the semiconductor device, wherein the active region has a second surface (because of the forming 30) topography variation less than the first surface topography variation after the annealing [0048], and wherein the semiconductor capping layer (20a → 20a/30) is thickened by the annealing; and forming a part of a gate structure [0056] over the active region after the annealing. Re claim 19, Bao teaches the method of claim 18, wherein: the active region contains germanium oxide ([5a/5b]/20a of FIG. 3); and the annealing reduces a content of the germanium oxide in the active region (by forming layer 30 of FIG. 4). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 9-10, 11 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bao in view of KIM (Pub. No.: US 2017/0372971). Re claims 9-10, and 16-17, Bao teaches all the limitation of claim 7/14; and wherein the annealing process comprises: a spike annealing process with an annealing temperature in a range between about 800 ºC and about 900 ºC with 2 seconds or less [0048]. Bao fails to teach the limitation of claim 9/10 and 16-17. KIM teaches wherein the annealing process is performed at least in part by applying an inert gas [0140] (claim 9); and the annealing in the hydrogen atmosphere 720 may be carried out at a temperature ranging from 600 °C to 900 °C and a pressure ranging from 1 to 20 torr for 5 to 60 seconds [0141] (claims 10 and 17). wherein surfaces of the active region are smoother after the annealing process has been performed (FIG. 7D → 7E, ¶ [0145]) (claim 16). It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of increasing accuracy of an operation as taught by KIM, [0003]. In re claims 10 and 17, Bao and KIM differ from the claim invention by not disclosing n annealing temperature in a range between about 300 ºC and about 450 ºC (claim 10) and an annealing pressure in a range between about 50 torrs and about 760 torrs (both claims 10 and 17). However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997). Re claim 11, in the combination, Bao teaches the method of claim 1, further comprising trimming the active region before the forming of the capping layer; wherein: the active region has a first surface roughness after being trimmed (outside surface of 5a); the active region has a second surface roughness after the content of the germanium oxide has been reduced (interface between Si of 30 and Ge of 5a/5b, FIG. 4); and the second surface roughness is less than the first surface roughness (because the smoothness after annealing of KIM). Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bao in view of Zhou (Pub. No.: US 2019/0157066). Bao teaches all the limitation of claim 18; and wherein the trimming comprises: oxidizing portions (to form [5a/5b]/30) of the active region; and applying wet etching to the active region, thereby removing the oxidized portions of the active region (FIG. 5 → 6). Bao fails to teach using an acid for wet etching. Zhou teaches using an acid for wet etching [0076]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of effectively remove the byproduct as taught by Zhou. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONY TRAN/Primary Examiner, Art Unit 2821
Read full office action

Prosecution Timeline

Jul 25, 2024
Application Filed
Sep 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
70%
Grant Probability
99%
With Interview (+33.3%)
2y 9m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 884 resolved cases by this examiner. Grant probability derived from career allowance rate.

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