Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the application filed July 25, 2024. Claims 1-20 are currently pending.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. This application is a divisional application of U.S. Patent Application No. 17/703,710, filed March 24, 2022, and issued as U.S. Pat. No. 12,347,770 on July 1, 2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 25, 2024 has been placed in the application file and is being considered by the examiner.
Drawings
The drawings filed with the application on July 25, 2024 are accepted.
Claim Objections
Claims 1 and 11 are objected to because of the following informalities: claim 1 recites, inter alia, “forming a second opening through the second dielectric layer, the fourth ESL, and the fourth ESL”. The phrase “and the fourth ESL” appears to have been inadvertently duplicated.
Claim 5 is objected to because of the following informalities: claim 5 recites, inter alia, “wherein the second ESL and the fourth ESL a nitrogen-free dielectric material”. The word “comprise” appears to have been inadvertently omitted.
Claim 12 is objected to because of the following informalities: claim 12 recites, inter alia, “wherein the resistive layer comprises the resistive layer comprises”. The phrase “the resistive layer comprises” appears to have been inadvertently duplicated.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hao et al., US 2004/0157392 A1 (hereinafter Hao) in view of Wang et al., US 2008/0012138 A1 (hereinafter Wang) in view of Okada et al., US 2007/0278617 A1 (hereinafter Okada).
Regarding claim 1, Hao teaches: A method, comprising: forming a conductive feature in a first dielectric layer (Hao, FIG. 2D shows metal line 226 [the conductive feature] in insulating layer 222 [the first dielectric layer], [0019]);
depositing a first etch stop layer (ESL) (Hao, FIG. 2D, insulating thin film 240, [0023]) and a second ESL (Hao, FIG. 2D, insulating thin film 244, “insulating thin films 240, 244 … serve as etch stop layer,” [0023]) over top surfaces of the conductive feature and the first dielectric layer (Hao, FIG. 2D shows insulating thin film 240 [the first ESL] and insulating thin film 244 [the second ESL] over top surfaces of metal line 226 [the conductive feature] and insulating layer 222 [the first dielectric layer], [0023-0025]);
forming a first opening through the first ESL and the second ESL to expose the conductive feature (Hao, photolithography and etching process is conducted to form openings in insulating thin film 240 [the first ESL] and insulating thin film 244 [the second ESL], [0025]);
Hao is silent regarding: conformally depositing a breakdown layer over the first opening;
conformally depositing a resistive layer over the breakdown layer;
depositing a third ESL and a fourth ESL over the resistive layer;
patterning the second ESL, the breakdown layer, the resistive layer, the third ESL, and the fourth ESL to form a one-time-programmable (OTP) device region;
depositing a second dielectric layer over the OTP device region;
forming a second opening through the second dielectric layer, the fourth ESL, and the fourth ESL to expose the resistive layer; and
forming a contact feature in the second opening to electrically coupled to the resistive layer.
However, Wang, in disclosing a one-time-programmable anti-fuse, teaches: conformally depositing a breakdown layer over the first opening (Wang, FIGs. 5-9, insulation layer 134 [the breakdown layer] shown conformally deposited in opening 128 [the first opening] within region 100, [0031-0032; 0039-0040]);
conformally depositing a resistive layer over the breakdown layer (Wang, FIGs. 6-9, barrier layer 138 [the resistive layer] shown conformally deposited over insulation layer 134 [the breakdown layer] within region 100, [0039-0040]);
depositing a third ESL and a fourth ESL over the resistive layer (Wang, “etch stop layers (not shown) are formed between layers 22, 24 and 26,” [0027], the etch stop layer above layer 22 is analogous to the first ESL, the etch stop layer above layer 24 is analogous to the second ESL, the etch stop layer above layer 26 is analogous to the third ESL; “an additional photo resist (not shown),” [analogous to the fourth ESL] formed and patterned over barrier layer 138 [the resistive layer] [0027-0028]);
patterning the second ESL, the breakdown layer, the resistive layer, the third ESL, and the fourth ESL to form a one-time-programmable (OTP) device region (Wang, FIGs. 7- 8 show formation of the OTP anti-fuse cell 150 [the one-time-programmable (OTP) device region] resulting from the patterning, [0028; 0040-0045]);
depositing a second dielectric layer over the OTP device region (Wang, FIG. 8, inter-metal dielectric (IMD) layer 26 [the second dielectric layer] shown above region 100 [the one-time-programmable (OTP) device region], [0027]);
forming a second opening through the second dielectric layer, the fourth ESL, and the fourth ESL to expose the resistive layer (Wang, FIGs. 3-8, trench opening 130 [the second opening] formed in inter-metal dielectric (IMD) layer 26 [the second dielectric layer], “with the masking of an additional photo resist (not shown) [the fourth ESL], trench openings 130 [the second opening] and 230 are formed, preferably by an anisotropic etching cutting through trench IMD layer 26 [the second dielectric layer],” [0027-0028]; FIGs. 7-8 show upper surface of barrier layer 138 [the resistive layer] exposed after forming trench opening 130 [the second opening]); and
forming a contact feature in the second opening to electrically coupled to the resistive layer (Wang, FIGs. 3-8, metal line 142 [the contact feature] shown formed in trench opening 130 [the second opening] and electrically coupled to barrier layer 138 [the resistive layer], [0027-0028; 0036-0037]).
As recognized by Wang, the method of conformally depositing a breakdown layer over the first opening; conformally depositing a resistive layer over the breakdown layer; depositing a third ESL and a fourth ESL over the resistive layer; patterning the second ESL, the breakdown layer, the resistive layer, the third ESL, and the fourth ESL to form a one-time-programmable (OTP) device region; depositing a second dielectric layer over the OTP device region; forming a second opening through the second dielectric layer, the fourth ESL, and the fourth ESL to expose the resistive layer; and forming a contact feature in the second opening to electrically coupled to the resistive layer was known in the art before the effective filing date of the claimed invention.
Additionally, although Wang describes the structure of the first through fourth etch stop layer (ESL), Wang does not provide any figures showing them. However, such features were known to one of ordinary skill in the art. For example, Okada, in the same field of endeavor, discloses a fuse formed on a semiconductor substrate, including a first ESL (Okada, FIG. 5A, first etch stop film 302, [0074]), a second ESL (Okada, FIG. 5A, second etch stop film 308, [0074]), a third ESL (Okada, FIG. 5A, third etch stop film 312, [0074]), and a fourth ESL (Okada, FIG. 5A, fourth etch stop film 318, [0074]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Hao with the teachings of Wang and Okada, and such a combination of known elements would have yielded predictable results with a high likelihood of success and without undue experimentation. The motivation for doing so would be, as recognized by Wang, to form an OTP anti-fuse cell using a damascene process resulting in improved manufacturing efficiency and reduced write voltage, thereby improving device performance and reliability.
Regarding claim 2, Hao in view of Wang and further in view of Okada teaches: The method of claim 1, wherein the breakdown layer (Wang, FIGs. 5-9, insulation layer 134, [0030]) comprises hafnium oxide (Wang, [0030]), aluminum oxide, aluminum nitride, titanium oxide, hafnium zirconium oxide, tantalum oxide (Wang, [0030]), hafnium aluminum oxide, hafnium silicon oxide, zirconium oxide (Wang, [0030]), zirconium silicon oxide, lanthanum oxide, yttrium oxide, strontium titanium oxide (Wang, [0030]), barium titanium oxide, barium zirconium oxide, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, or hafnium titanium oxide.
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Wang include one or more of Applicant’s claimed alternative elements, for example, Wang teaches that the insulation layer [the breakdown layer] may comprise: “oxides, nitrides, oxynitrides, … HfO2 [hafnium oxide], Ta2O5 [tantalum oxide], ZrO2 [zirconium oxide], Pr2O3, TiO2 [titanium oxide], SrTiO3 [strontium titanium oxide], and the like,” (Wang, [0030]).
Regarding claim 3, Hao in view of Wang and further in view of Okada teaches: The method of claim 1, wherein the breakdown layer (Wang, FIGs. 5-9, insulation layer 134, [0030]) comprises a thickness between 10 Å and about 100 Å (Wang, FIGs. 5-9, insulation layer 134 [the breakdown layer] “has a thickness of less than about 1000 Å, and more preferably between about 50 Å and about 200 Å,” [0031]).
Regarding claim 4, Hao in view of Wang and further in view of Okada teaches: The method of claim 1, wherein the resistive layer (Wang, FIGs. 6-9, barrier layer 138) comprises titanium nitride (TiN) (Wang, [0026]), tantalum nitride (TaN) (Wang, [0026]), tungsten nitride (WN), or a combination thereof.
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Wang include one or more of Applicant’s claimed alternative elements, for example, Wang teaches that the barrier layer [the resistive layer] may comprise: “titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and other alternatives,” (Wang, [0026; 0035]).
Regarding claim 5, Hao in view of Wang and further in view of Okada teaches: The method of claim 1, … wherein the second ESL and the fourth ESL comprise a nitrogen-free dielectric material (Okada, “the second etch stop film 308 [the second ESL] and the fourth etch stop film 318 [the fourth ESL] may be composed of, for example … SiC, SiOF,” [0083]). Hao in view of Wang and further in view of Okada does not explicitly teach: wherein the first ESL and the third ESL comprise aluminum oxide, aluminum nitride, or hydrogen-containing silicon carbonitride.
However, a person having ordinary skill in the art would have applied the knowledge generally available to one of ordinary skill in the art, insofar as selecting appropriate materials for the first ESL and the third ESL. For example, Wang teaches a metal nitride layer, i.e., aluminum nitride, used for patterning, i.e., as an etch stop layer, (Wang, [0038]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Wang, Hao, and Okada, insofar as selecting aluminum nitride as the material for the first ESL and third ESL layers, because aluminum nitride was known in the art as being an effective etch stop layer material, and would have yielded predicable results without undue experimentation.
Regarding claim 6, Hao in view of Wang and further in view of Okada teaches: The method of claim 5, wherein the nitrogen-free dielectric material comprises silicon oxide (Okada, “the second etch stop film 308 [the second ESL] and the fourth etch stop film 318 [the fourth ESL] may be composed of, for example … SiOF,” i.e., silicon oxyfluoride, comprising silicon oxide, [0083]) or hydrogen-containing silicon oxycarbide.
Regarding claim 7, Hao in view of Wang and further in view of Okada teaches: The method of claim 1, wherein the patterning does not comprise exposing or etching the first ESL (Wang, FIGs. 7- 8 show formation of the OTP anti-fuse cell 150 [the one-time-programmable (OTP) device region] resulting from the patterning; the etch stop layer (not shown) between layers 22 and 24 [the first ESL] is shown beneath barrier layer 138 [the resistive layer] and is not exposed or etched during the patterning, [0027-0028; 0040-0045]).
Additionally, because Applicant’s specification is entirely silent on how the claimed step of patterning does not comprise exposing or etching the first ESL is achieved, that silence suggests that figuring out how to achieve that step or function is within the ordinary skill in the art. See MPEP 2141.03.
Regarding claim 8, Hao in view of Wang and further in view of Okada teaches: The method of claim 1, wherein the contact feature comprises a via portion and line portion over the via portion (Wang, FIG. 8, connecting via 140 [the via portion] and metal line 142 [the line portion], [0036]).
Regarding claim 11, Hao teaches: A method, comprising: forming a conductive feature in a first dielectric layer (Hao, FIG. 2D shows metal line 226 [the conductive feature] in insulating layer 222 [the first dielectric layer], [0019]);
depositing a first etch stop layer (ESL) (Hao, FIG. 2D, insulating thin film 240, [0023]) and a second ESL (Hao, FIG. 2D, insulating thin film 244, “insulating thin films 240, 244 … serve as etch stop layer,” [0023]) over top surfaces of the conductive feature and the first dielectric layer (Hao, FIG. 2D shows insulating thin film 240 [the first ESL] and insulating thin film 244 [the second ESL] over top surfaces of metal line 226 [the conductive feature] and insulating layer 222 [the first dielectric layer], [0023-0025]);
forming a first opening through the first ESL and the second ESL to expose the conductive feature (Hao, photolithography and etching process is conducted to form openings in insulating thin film 240 [the first ESL] and insulating thin film 244 [the second ESL], [0025]);
Hao is silent regarding: conformally depositing a breakdown layer over the first opening;
conformally depositing a resistive layer over the breakdown layer;
depositing a third ESL and a fourth ESL over the resistive layer;
etching the second ESL, the breakdown layer, the resistive layer, the third ESL, and the fourth ESL to form recesses that define a one-time-programmable (OTP) device region vertically overlapping with the conductive feature;
depositing a second dielectric layer over the OTP device region;
forming a second opening through the second dielectric layer, the fourth ESL, and the fourth ESL to expose the resistive layer; and
forming a contact feature in the second opening to electrically coupled to the resistive layer,
wherein a composition of the resistive layer is different from a composition of the conductive feature.
However, Wang, in disclosing a one-time-programmable anti-fuse, teaches: conformally depositing a breakdown layer over the first opening (Wang, FIGs. 5-9, insulation layer 134 [the breakdown layer] shown conformally deposited in opening 128 [the first opening] within region 100, [0031-0032; 0039-0040]);
conformally depositing a resistive layer over the breakdown layer (Wang, FIGs. 6-9, barrier layer 138 [the resistive layer] shown conformally deposited over insulation layer 134 [the breakdown layer] within region 100, [0039-0040]);
depositing a third ESL and a fourth ESL over the resistive layer (Wang, “etch stop layers (not shown) are formed between layers 22, 24 and 26,” [0027], the etch stop layer above layer 22 is analogous to the first ESL, the etch stop layer above layer 24 is analogous to the second ESL, the etch stop layer above layer 26 is analogous to the third ESL; “an additional photo resist (not shown),” [analogous to the fourth ESL] formed and patterned over barrier layer 138 [the resistive layer] [0027-0028]);
etching the second ESL, the breakdown layer, the resistive layer, the third ESL, and the fourth ESL to form recesses that define a one-time-programmable (OTP) device region vertically overlapping with the conductive feature (Wang, FIGs. 7- 8 show formation of the OTP anti-fuse cell 150 [the one-time-programmable (OTP) device region] defined by openings 128 and 130 [the recesses] vertically overlapping with metal lines 102 [the conductive feature] resulting from the etching, [0027-0028; 0040-0045]);
depositing a second dielectric layer over the OTP device region (Wang, FIG. 8, inter-metal dielectric (IMD) layer 26 [the second dielectric layer] shown above region 100 [the one-time-programmable (OTP) device region], [0027]);
forming a second opening through the second dielectric layer, the fourth ESL, and the fourth ESL to expose the resistive layer (Wang, FIGs. 3-8, trench opening 130 [the second opening] formed in inter-metal dielectric (IMD) layer 26 [the second dielectric layer], “with the masking of an additional photo resist (not shown) [the fourth ESL], trench openings 130 [the second opening] and 230 are formed, preferably by an anisotropic etching cutting through trench IMD layer 26 [the second dielectric layer],” [0027-0028]; FIGs. 7-8 show upper surface of barrier layer 138 [the resistive layer] exposed after forming trench opening 130 [the second opening]); and
forming a contact feature in the second opening to electrically coupled to the resistive layer (Wang, FIGs. 3-8, metal line 142 [the contact feature] shown formed in trench opening 130 [the second opening] and electrically coupled to barrier layer 138 [the resistive layer], [0027-0028; 0036-0037]),
wherein a composition of the resistive layer (Wang, the barrier layer [the resistive layer] may comprise: “titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and other alternatives,” (Wang, [0026; 0035]) is different from a composition of the conductive feature (Wang, metal line 102 [the conductive feature] comprises “copper or copper alloys, although they may comprise other metallic materials such as aluminum, silver, gold, and the like,” [0026]).
As recognized by Wang, the method of conformally depositing a breakdown layer over the first opening; conformally depositing a resistive layer over the breakdown layer; depositing a third ESL and a fourth ESL over the resistive layer; etching the second ESL, the breakdown layer, the resistive layer, the third ESL, and the fourth ESL to form recesses that define a one-time-programmable (OTP) device region vertically overlapping with the conductive feature; depositing a second dielectric layer over the OTP device region; forming a second opening through the second dielectric layer, the fourth ESL, and the fourth ESL to expose the resistive layer; and forming a contact feature in the second opening to electrically coupled to the resistive layer, wherein a composition of the resistive layer is different from a composition of the conductive feature was known in the art before the effective filing date of the claimed invention.
Additionally, although Wang describes the structure of the first through fourth etch stop layer (ESL), Wang does not provide any figures showing them. However, such features were known to one of ordinary skill in the art. For example, Okada, in the same field of endeavor, discloses a fuse formed on a semiconductor substrate, including a first ESL (Okada, FIG. 5A, first etch stop film 302, [0074]), a second ESL (Okada, FIG. 5A, second etch stop film 308, [0074]), a third ESL (Okada, FIG. 5A, third etch stop film 312, [0074]), and a fourth ESL (Okada, FIG. 5A, fourth etch stop film 318, [0074]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Hao with the teachings of Wang and Okada, and such a combination of known elements would have yielded predictable results with a high likelihood of success and without undue experimentation. The motivation for doing so would be, as recognized by Wang, to form an OTP anti-fuse cell using a damascene process resulting in improved manufacturing efficiency and reduced write voltage, thereby improving device performance and reliability.
Regarding claim 12, Hao in view of Wang and further in view of Okada teaches: The method of claim 11, wherein the resistive layer (Wang, FIGs. 6-9, barrier layer 138) comprises titanium nitride (TiN) (Wang, [0026]), tantalum nitride (TaN) (Wang, [0026]), tungsten nitride (WN), or a combination thereof, and wherein the conductive feature comprises aluminum (Al), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co), copper (Cu), or a combination thereof (Hao, FIG. 2D, metal line 226, copper, [0019]; Wang, metal line 102 [the conductive feature] comprises “copper or copper alloys, although they may comprise other metallic materials such as aluminum, silver, gold, and the like,” [0026]).
Regarding claim 13, Hao in view of Wang and further in view of Okada teaches: The method of claim 11, wherein the breakdown layer (Wang, FIGs. 5-9, insulation layer 134, [0030]) comprises hafnium oxide (Wang, [0030]), aluminum oxide, aluminum nitride, titanium oxide, hafnium zirconium oxide, tantalum oxide (Wang, [0030]), hafnium aluminum oxide, hafnium silicon oxide, zirconium oxide (Wang, [0030]), zirconium silicon oxide, lanthanum oxide, yttrium oxide, strontium titanium oxide (Wang, [0030]), barium titanium oxide, barium zirconium oxide, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, or hafnium titanium oxide.
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Wang include one or more of Applicant’s claimed alternative elements, for example, Wang teaches that the insulation layer [the breakdown layer] may comprise: “oxides, nitrides, oxynitrides, … HfO2 [hafnium oxide], Ta2O5 [tantalum oxide], ZrO2 [zirconium oxide], Pr2O3, TiO2 [titanium oxide], SrTiO3 [strontium titanium oxide], and the like,” (Wang, [0030]).
Regarding claim 14, Hao in view of Wang and further in view of Okada teaches: The method of claim 13, wherein the breakdown layer (Wang, FIGs. 5-9, insulation layer 134, [0030]) comprises a thickness between 10 Å and about 100 Å (Wang, FIGs. 5-9, insulation layer 134 [the breakdown layer] “has a thickness of less than about 1000 Å, and more preferably between about 50 Å and about 200 Å,” [0031]).
Regarding claim 15, Hao in view of Wang and further in view of Okada teaches: The method of claim 11, wherein the recesses terminate in the second ESL (Wang, see FIGs. 7- 8, openings 128 and 130 [the recesses] have upper and lower boundaries, i.e., terminate, in the etch stop layer (not shown) between layers 24 and 26 [the second ESL], [0027-0028]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hao in view of Wang
Regarding claim 17, Hao teaches: A method, comprising: receiving a workpiece comprising: a first dielectric layer (Hao, FIGs. 2A-2D, insulating layer 222 [the first dielectric layer] shown on semiconductor wafer layer 220 formed on substrate [the workpiece], [0019]) ,
a first conductive feature and a second conductive feature in the first dielectric layer (Hao, FIG. 2D shows metal line 226 [the first conductive feature] and metal line 224 [the second conductive feature] in insulating layer 222 [the first dielectric layer], [0019]),
a first etch stop layer (ESL) disposed over the first dielectric layer, the first conductive feature and the second conductive feature (Hao, FIG. 2D, insulating thin film 240, [0023]),
a second ESL disposed over the first ESL (Hao, FIG. 2D, insulating thin film 244, “insulating thin films 240, 244 … serve as etch stop layer,” [0023]), and
a second dielectric layer over the second ESL (Hao, FIG. 2D, insulating thin film 246, “insulating layers 242, 246, which serve as the inter-metal dielectric layer”, i.e., a dielectric layer, [0023]);
forming a first opening through the second dielectric layer, the second ESL and the first ESL to expose the first conductive feature (Hao, photolithography and etching process is conducted to form openings in insulating thin film 246 [the second dielectric layer], insulating thin film 240 [the first ESL] and insulating thin film 244 [the second ESL], [0025]);
Hao is silent regarding: conformally depositing an antifuse layer over the first opening;
conformally depositing a conductive layer over the antifuse layer;
forming a top electrode over the conductive layer such that the top electrode is spaced apart from the second dielectric layer, the second ESL and the first ESL by the antifuse layer and the conductive layer;
after the forming of the top electrode, forming a second opening through the second dielectric layer, the second ESL and the first ESL to expose the second conductive feature; and
forming a via and a conductive line in the second opening.
However, Wang, in disclosing a one-time-programmable anti-fuse, teaches: conformally depositing an antifuse layer over the first opening (Wang, FIGs. 5-9, insulation layer 134 [the antifuse layer] shown conformally deposited over opening 128 [the first opening] within region 100, “to program the OTP anti-fuse cell 150, a voltage may be applied between the two electrodes, causing a breakdown in insulation layer 134 [the antifuse layer],” [0031-0032; 0039-0040]);
conformally depositing a conductive layer over the antifuse layer (Wang, FIGs. 6-9, barrier layer 138 [the conductive layer] shown conformally deposited over insulation layer 134 [the antifuse layer] within region 100, [0039-0040]);
forming a top electrode over the conductive layer such that the top electrode is spaced apart from the second dielectric layer, the second ESL and the first ESL by the antifuse layer and the conductive layer (Wang, FIGs. 3-8, metal line 142 [the top electrode] shown formed over barrier layer 138 [the conductive layer] and spaced apart from the etch stop layer (not shown) between layers 22 and 24 [the first ESL], the etch stop layer (not shown) between layers 24 and 26 [the second ESL], [0027-0028], and dielectric layer 24 [the second dielectric layer] by the barrier layer 138 [the conductive layer], and insulation layer 134 [the antifuse layer], [0027-0028; 0036-0037]);
after the forming of the top electrode, forming a second opening through the second dielectric layer, the second ESL and the first ESL to expose the second conductive feature (Wang, FIGs. 3-8 show openings 228 and 230 [the second opening] formed through dielectric layer 24 [the second dielectric layer], the etch stop layer (not shown) between layers 22 and 24 [the first ESL], the etch stop layer (not shown) between layers 24 and 26 [the second ESL], to expose metal lines 202 [the second conductive feature]; see also Hao, FIG. 2C and associated text); and
forming a via and a conductive line in the second opening (Wang, FIG. 8 shows via 240 [the via] and metal line 242 [the conductive line] formed in openings 228 and 230 [the second opening], [0036]).
As recognized by Wang, the method of conformally depositing an antifuse layer over the first opening; conformally depositing a conductive layer over the antifuse layer; forming a top electrode over the conductive layer such that the top electrode is spaced apart from the second dielectric layer, the second ESL and the first ESL by the antifuse layer and the conductive layer; after the forming of the top electrode, forming a second opening through the second dielectric layer, the second ESL and the first ESL to expose the second conductive feature; and forming a via and a conductive line in the second opening was known in the art before the effective filing date of the claimed invention. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Hao with the teachings of Wang, and such a combination of known elements would have yielded predictable results with a high likelihood of success and without undue experimentation. The motivation for doing so would be, as recognized by Wang, to form an OTP anti-fuse cell using a damascene process resulting in improved manufacturing efficiency and reduced write voltage, thereby improving device performance and reliability.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hao in view of Wang and further in view of Tsau, US 2005/0161765 A1 (hereinafter Tsau).
Regarding claim 18, Hao in view of Wang teaches: The method of claim 17, as discussed above. Hao in view of Wang is silent regarding: wherein the forming of the first opening comprises: depositing a hard mask layer over the second dielectric layer; patterning the hard mask layer to form a patterned hard mask layer; and etching the second dielectric layer, the second ESL and the first ESL using the patterned hard mask layer as an etch mask.
However, Tsau, in the same field of endeavor, teaches that it was known in the art before the effective filing date of the claimed invention to form a via opening through two layers of dielectric by masking and etching through patterned hard mask layer, thereby reducing production costs and minimizing processing steps during device manufacturing (Tsau, [0066]). Therefore, it would have been obvious to a person having ordinary skill in the art to apply the teachings of Tsau to the teachings of Hao in view of Wang, arriving at Applicant’s claimed invention with a high likelihood of success and without undue experimentation. The motivation to do so would be to provide improved control of the etch process thereby increasing manufacturing yield while improving device performance and reliability.
Regarding claim 19, Hao in view of Wang and further in view of Tsau teaches: The method of claim 18, wherein the conformally depositing of the antifuse layer comprises depositing the antifuse layer (Wang, FIGs. 5-9, insulation layer 134 [the antifuse layer]) on the patterned hard mask layer (Tsau, “a hard mask or etch stop layer, deposited by standard deposition techniques, can be employed as the insulator in a capacitor-like structure, including capacitors and antifuses,” [0066]).
Claims 9, 10, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hao in view of Wang and further in view of Okada and further in view of Lian et al., US 2020/0328110 A1 (hereinafter Lian).
Regarding claim 9, Hao in view of Wang and further in view of Okada teaches: The method of claim 1, as discussed above. Hao in view of Wang and further in view of Okada is silent regarding: further comprising: before the conformally depositing of the breakdown layer (Wang, FIGs. 5-9, insulation layer 134, [0030]), performing a wet clean process to clean the first opening; and performing a bake process.
However, Lian, in the same field of endeavor, teaches that after an etching process to form an opening, it is advantageous to perform “a wet clean process, a baking process, and a post-clean process … after the wet clean process, a mild bake process can be performed to drive moisture out,” before continuing with subsequent processing steps such as conformal deposition (Lian, [0019-0021]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hao in view of Wang and Okada with the teachings of Lian, arriving at Applicant’s claimed method with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Lian, clean the opening of residue following etching and to drive moisture out following cleaning, thereby improving process quality, device performance and reliability.
Regarding claim 10, Hao in view of Wang and further in view of Okada and further in view of Lian teaches: The method of claim 9, wherein the bake process comprises a temperature between about 250 °C and about 350 °C (Lian, “the mild bake process [the bake process] can be performed at a temperature in a range from about 200° C. to about 400° C., such as about 300° C., for a duration in a range from about 5 minutes to about 10 minutes,” [0021]).
Regarding claim 16, Hao in view of Wang and further in view of Okada and further in view of Lian teaches: The method of claim 11, further comprising: before the conformally depositing of the breakdown layer (Wang, FIGs. 5-9, insulation layer 134, [0030]), performing a wet clean process to clean the first opening; and performing a bake process (Lian, “a wet clean process is implemented to remove residue from the RIE process [to clean the first opening],” [0020]; “after the wet clean process, a mild bake process can be performed to drive moisture out,” [0021]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hao in view of Wang and further in view of Lian.
Regarding claim 20, Hao in view of Wang and further in view of Lian teaches: The method of claim 17, further comprising: before the conformally depositing the antifuse layer (Wang, FIGs. 5-9, insulation layer 134, [0030]), baking the workpiece.
As discussed above, Lian teaches that after an etch process to form an opening, it is advantageous to perform “a wet clean process, a baking process, and a post-clean process … after the wet clean process, a mild bake process can be performed to drive moisture out,” before continuing with subsequent processing steps such as conformal deposition (Lian, [0019-0021]; 0032). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hao in view of Wang with the teachings of Lian, arriving at Applicant’s claimed method with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Lian, to drive moisture out before depositing conformal fill, thereby improving process quality, device performance and reliability.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. The cited prior art discloses similar materials, devices, and methods.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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