DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application.
Claim Objections
Claims 12 and 14 are objected to because of the following informalities:
Regarding claim 12, it recites “an outer portion of the bottom electrode”, it should read “the outer portion of the bottom electrode”, or another appropriate correction.
Regarding claim 14, it recites “wherein layer stack”, it should read “wherein the layer stack”, or another appropriate correction.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-5, 8, 19, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, it recites the limitation “the bottom of the opening” in line 5. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “a bottom of the opening”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter.
Regarding claims 3-5, the claims depend from rejected claim 2, includes all limitations of claim 2 and therefore are rejected for the same reason. The claims will be examined on the basis of interpretation of the rejected claim hereafter.
Regarding claim 3, it recites the limitation “the second dielectric layer” in line 2. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “the second dielectric material layer”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter.
Regarding claim 5, it recites the limitations “an opening in the dielectric material layer” in line 2 and “the opening” in line 4. Claim 2, from which claim 5 depends, previously recites “an opening through the second dielectric material layer”, and it is unclear whether “the opening” recited in claim 5 refers to “the opening through the second dielectric material layer” of claim 1 or the “opening in the dielectric material layer”, or to a different opening, therefore, there is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “the opening through the second dielectric material layer” in line 4, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter.
Regarding claim 8, it recites the limitation “following the etching process” in line 1. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “following recessing the upper surface of the dielectric material layer relative to the upper surface of the bottom electrode”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter.
Regarding claim 19, it recites the limitation “the second dielectric layer” in lines 2 and 3. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “the second dielectric material layer”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter.
Regarding claim 20, the claim depends from rejected claim 19, includes all limitations of claim 19 and therefore is rejected for the same reason. The claim will be examined on the basis of interpretation of the rejected claim hereafter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al (US 20200227634 A1, hereafter Hung).
Regarding claim 16, Hung discloses: A method of forming a resistive memory device (Hung 200, fig 1A-B, 2A-P, ¶0049), comprising:
recessing an upper surface of a dielectric material layer (Hung 206, ¶0020) laterally surrounding a bottom electrode (Hung 208, 212, ¶0023-0027) to expose a corner portion of the bottom electrode (Hung 208A, 208B, 212A, fig 2G, corner formed at 208A and 208B)(Hung 114, fig 1A, 2F-G, ¶0028, 206A becoming 206B);
forming a layer stack (Hung 216, 218, 220, 222) comprising a switching layer (Hung 218, ¶0002, 0034-0035, “variable resistive material layer”, at least capable of switching between high and low resistance) and a top electrode (Hung 220, ¶0039-0041) over the corner portion (Hung 120, 122, 2J-L, ¶0034-0039); and
forming a conductive via (Hung 234, ¶0049, claims 4 and 13) contacting the layer stack (Hung 132, fig 1B, 2P, ¶0049-0051).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US 20200227634 A1, hereafter Hung) in view of Higano et al (US 20150109093 A1, as cited in the IDS dated 05/06/2026, hereafter Higano).
Regarding claim 1, Hung teaches: A method of fabricating a resistive memory device (Hung 200, fig 1A-B, 2A-P, ¶0049), comprising:
forming a bottom electrode (Hung 208, 212, ¶0023-0027) in a dielectric material layer (Hung 206, ¶0020)(Hung 104-112, fig 1A, 2C-G, ¶0019-0027);
recessing an upper surface of the dielectric material layer (Hung 206A, fig 2G, ¶0023) relative to an upper surface of the bottom electrode (Hung 208A, 212A, fig 2G, ¶0027) to expose a side surface of the bottom electrode (Hung 208B, fig 2G, ¶0028)(Hung 114, fig 1A, 2F-G, ¶0028, 206A becoming 206B);
forming a switching layer (Hung 218, ¶0002, 0034-0035, “variable resistive material layer”, at least capable of switching between high and low resistance) over the upper surface of the dielectric material layer and the exposed side surface and the upper surface of the bottom electrode (Hung 120, fig 1B, 2J, ¶0034), the switching layer comprising a first horizontal portion (Hung 218-4, 218-5, ¶0034) over the upper surface of the dielectric material layer (Hung fig 2J, ¶0034), a second horizontal portion (Hung 218-1, ¶0034) over the upper surface of the bottom electrode (Hung fig 2J, ¶0034), and a first vertical portion (Hung 218-2, 218-3, ¶0034) over the exposed side surface of the bottom electrode between the first horizontal portion and the second horizontal portion of the switching layer (Hung fig 2J, ¶0034);
forming a top electrode (Hung 220, ¶0039-0041) over the switching layer (Hung 122, fig 1B, 2K, ¶0039), the top electrode comprising a first horizontal portion (Hung 220-4, 220-5, ¶0039) over the first horizontal portion of the switching layer (Hung fig 2K, ¶0039), a second horizontal portion (Hung 220-1, ¶0039) over the second horizontal portion of the switching layer (Hung fig 2K, ¶0039), and a first vertical portion (Hung 220-2, 220-3, ¶0039) over the first vertical portion of the switching layer between the first horizontal portion and the second horizontal portion of the top electrode (Hung fig 2K, ¶0039); and
forming a conductive via (Hung 234, ¶0049, claims 4 and 13) over the top electrode (Hung 132, fig 1B, 2P, ¶0049-0051).
Hung does not teach: wherein the conductive via contacts the first horizontal portion, the second horizontal portion, and the first vertical portion of the top electrode.
Higano, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a conductive via (Higano 15, ¶0062, under a broadest reasonable interpretation (BRI) of a “via”) over a top electrode (Higano 14, ¶0061-0062)(Higano A5, 6A-C, 19A-C, ¶0072, ¶0117), wherein the conductive via contacts a first horizontal portion (Higano fig 6C, 19C, horizontal portions of 14 at bottom of 19, adjacent to 11, similar to Hung 220-4, 220-5), a second horizontal portion (Higano fig 6C, 19C, horizontal portion of 14 directly above a top surface of 11, similar to Hung 220-1), and a first vertical portion (Higano fig 6C, 19C, vertical portions of 14 adjacent to 11, similar to Hung 220-2, 220-3) of the top electrode (Higano fig 6C, 9B, 19C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Hung to include forming the conductive via such that it “contacts the first horizontal portion, the second horizontal portion, and the first vertical portion of the top electrode”, as taught by Higano, in order to increase the contact area between the conductive via and the top electrode, thereby reducing the resistance and the voltage to from and switch the switching layer (Higano ¶0066, 0091-0097).
Regarding claim 6, Hung in view of Higano teaches: The method of claim 1, wherein the switching layer (Hung 218) comprises a solid-state dielectric material (Hung ¶0035-0038, “218 includes ZrO2… NiO, TiO2, HfO, ZrO, ZnO, WO3, CoO, Nb2O5, Fe2O3, CuO, CrO2, SrZrO3”, applicant similarly discloses that materials suitable as “a solid-state dielectric material” include “titanium dioxide (TiO2), hafnium dioxide (HFO2), … zirconium dioxide (ZrO2), … nickel oxide (NiO), zinc oxide (ZnO)”) that is switchable between a High Resistance State (HRS) and a Low Resistance State (LRS)(Hung ¶0002, 0034-0035, “variable resistive material layer 218 includes material characterized to show reversible resistance variance … may be changed into a conductor or an insulator”, at least capable thereof).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US 20200227634 A1, hereafter Hung) in view of Higano et al (US 20150109093 A1, as cited in the IDS dated 05/06/2026, hereafter Higano), as applied to claim 1 above, and further in view of Sung et al (US 20170222128 A1, hereafter Sung).
Regarding claim 2, Hung in view of Higano teaches: The method of claim 1, wherein forming the conductive via (Hung 234 as modified by Higano 15)(Hung 132 as modified by Higano) comprises:
forming a second dielectric material layer (Hung 232, ¶0047-0048) over the top electrode (Hung 220)(Hung 130, fig 1B, 2O, ¶0047);
forming an opening (Hung ¶0050) through the second dielectric material layer to expose the second horizontal portion of the top electrode (Hung 220-1) at the bottom of the opening (as best understood to mean “a bottom of the opening)(Hung 132, fig 1B, 2P, ¶0049-0050); and
depositing an electrically conductive material (Hung ¶0050, “Cu”) within the opening to form the conductive via (Hung 132, fig 1B, 2P, ¶0049-0050).
Hung in view of Higano does not explicitly teach: forming an opening through the second dielectric material layer to expose the first vertical portion, and a part of the first horizontal portion of the top electrode at the bottom of the opening.
Sung, in the same field of endeavor of semiconductor device manufacturing, teaches: forming an opening (Sung 123A, ¶0059, under a BRI of an opening) through a second dielectric material layer (Sung 125, ¶0056-0058) to expose a second horizontal portion and a first vertical portion of a top electrode (Sung 133, ¶0059) at a bottom of the opening (Sung ¶0059, fig 14).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Hung in view of Higano such that the opening formed in the second dielectric material layer exposed the second horizontal portion and the first vertical portion of the top electrode, as taught by Sung, and further to expose the first horizontal portion of the top electrode at the bottom of the opening, in order to expose a larger surface are between the top electrode and conductive via, thereby ensuring a sufficient contact interface and/or lowering series resistance (Sung ¶0025).
Regarding claim 3, Hung in view of Higano and Sung teaches: The method of claim 2, further comprising:
forming a passivation layer (Hung 230, ¶0046, “silicon nitride”, similar to Sung 127C, ¶0038, “silicon nitride”, applicant discloses that suitable materials for a passivation layer includes “silicon nitride”, spec ¶0142) over the top electrode (Hung 220)(Hung 128, fig 1B, ¶0045-0046, similar to Sung fig 14), wherein the second dielectric layer (as best understood to mean “the second dielectric material layer”)(Hung 232, similar to Sung 125) is formed over the passivation layer (Hung fig 2O, ¶0047, similar to Sung fig 14), and wherein forming the opening (Hung 132 as modified by Sung) comprises forming the opening (Hung as modified by Sung 123A) through the second dielectric material layer and the passivation layer to expose the second horizontal portion (Hung 220-1), the first vertical portion (Hung 220-2, 220-3), and a part of the first horizontal portion (Hung 220-4, 220-5) of the top electrode at the bottom of the opening (Hung 132 as modified by Sung, similar to Sung fig 14, ¶0059).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US 20200227634 A1, hereafter Hung) in view of Higano et al (US 20150109093 A1, as cited in the IDS dated 05/06/2026, hereafter Higano), as applied to claim 1 above, and further in view of Ando et al (US 20190165269 A1, hereafter Ando).
Regarding claim 7, Hung in view of Higano teaches: The method of claim 1.
Hung in view of Higano does not explicitly teach: wherein recessing the upper surface of the dielectric material layer relative to the upper surface of the bottom electrode comprises etching the dielectric material layer and the bottom electrode using an etch chemistry that has a higher etch selectivity for the dielectric material layer relative to the bottom electrode.
Higano further teaches: recessing an upper surface of a dielectric material layer (Higano 10, ¶0061) relative to an upper surface of a bottom electrode (Higano 11, ¶0061)(Higano ¶0070, 0080, fig 5B, 18B).
Ando, in the same field of endeavor of semiconductor device manufacturing, teaches: recessing an upper surface of a dielectric material layer (Ando 2, ¶0042) relative to an upper surface of a bottom electrode (Ando 10, ¶0042)(Ando fig 4, 5, ¶0042-0043) comprises etching the dielectric material layer and the bottom electrode using an etch chemistry that has a higher etch selectivity for the dielectric material layer relative to the bottom electrode (Ando ¶0042, “etchant of the etch process may be selected to remove the material of the first dielectric layer 2 without etching, i.e., removing, the material of the lower electrode 10”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the recessing method of the upper surface of the dielectric material layer relative to the upper surface of the bottom electrode of Hung in view of Higano such that “etching the dielectric material layer and the bottom electrode using an etch chemistry that has a higher etch selectivity for the dielectric material layer relative to the bottom electrode”, as taught by Ando, in order to eliminate the need for a patterning mask to recess the dielectric material layer and/or in order to provide for corners on the bottom electrode, thereby lowering the forming voltage of the device and/or reducing device variability (Ando ¶0016, 0042).
Regarding claim 8, Hung in view of Higano and Ando, in at least one embodiment, teaches: The method of claim 7, wherein following the etching process (as best understood to mean “after recessing the upper surface of the dielectric material layer relative to the upper surface of the bottom electrode”)(Hung 114 as modified by Ando), the upper surface of the dielectric material layer (Hung 206B, similar to Ando 2) is recessed relative to the upper surface of the bottom electrode (Hung 208A, 212A, similar to Ando 10) by at least 3 nm (Ando H2, ¶0043, “10 nm to 50 nm”) and an angle between the upper surface of the dielectric material layer and the side surface of the bottom electrode (Hung 208B) is less than 90° (Hung ¶0031, layers are formed “conformal and thin” having profile 215 which includes an acute angle between portions of 206B, 2XX-4 and 2XX-2, and between portions of 208B, 2XX-5 and 2XX-3).
Claims 9, 10, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US 20200227634 A1, hereafter Hung) in view of Chung et al (US 20100019218 A1, hereafter Chung).
Regarding claim 9, Hung teaches: A method of fabricating a resistive memory device (Hung 200, fig 1A-B, 2A-P, ¶0049), comprising:
forming a bottom electrode (Hung 208, 212, ¶0023-0027) in a dielectric material layer (Hung 206, ¶0020)(Hung 104-112, fig 1A, 2C-G, ¶0019-0027);
recessing an upper surface of the dielectric material layer (Hung 206A, fig 2G, ¶0023) relative to an upper surface of the bottom electrode (Hung 208A, 212A, fig 2G, ¶0027) to expose a side surface of the bottom electrode (Hung 208B, fig 2G, ¶0028)(Hung 114, fig 1A, 2F-G, ¶0028, 206A becoming 206B);
forming a layer stack (Hung 216, 218, 220, 222) comprising a switching layer (Hung 218, ¶0002, 0034-0035, “variable resistive material layer”, at least capable of switching between high and low resistance) and a top electrode (Hung 220, ¶0039-0041) over the dielectric material layer and the bottom electrode (Hung 120, 122, 2J-L, ¶0034-0039); and
forming a conductive via (Hung 234, ¶0049, claims 4 and 13) contacting the layer stack (Hung 132, fig 1B, 2P, ¶0049-0051).
Hung does not teach: recessing a central portion of the bottom electrode relative to an outer portion of the bottom electrode.
Chung, in the same field of endeavor of semiconductor device manufacturing, teaches: recessing a central portion (Chung G, ¶0027, 0029) of a bottom electrode (Chung 22, 22A) relative to an outer portion (Chung F, ¶0029) of the bottom electrode (Chung fig 3D-E, ¶0017, 0027-0029).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Hung to “recessing a central portion of the bottom electrode relative to an outer portion of the bottom electrode”, as taught by Chung, in order to form peaks at the edges of the bottom electrode, thereby improving voltage/current distribution in the set/reset mode of the device (Chung ¶0008, 0022, 0029).
Regarding claim 10, Hung in view of Chung teaches: The method of claim 9, wherein forming the bottom electrode (Hung 208, 212) in the dielectric material layer (Hung 206)(Hung 104-112) comprises:
forming an opening (Hung 207, ¶0021) in the dielectric material layer (Hung 106, fig 1A, 2C, ¶0021);
forming a first conductive material (Hung 208, ¶0024, 0026) over side surfaces and a bottom surface of the opening (Hung 108, fig 1A, 2D, ¶0023); and
forming a second conductive material (Hung 210, ¶0025-0026, 210 becoming 212) over the first conductive material and filling a remaining volume of the opening (Hung 110, fig 1A, 2E, ¶0025-0026).
Regarding claim 13, Hung in view of Chung teaches: The method of claim 9, wherein recessing the upper surface of the dielectric material layer (Hung 206A) relative to the upper surface of the bottom electrode (Hung 208A)(Hung 114) exposes an outer side surface of the bottom electrode (Hung 208B, fig 2G, ¶0028), and recessing the central portion (Hung 208A, 212A) of the bottom electrode relative to the outer portion of the bottom electrode (Hung as modified to include Chung G) exposes an interior side surface of the bottom electrode (Chung ¶0017, 0027, “surrounded by the edges”, under a BRI, the bottom electrode extending from its edges down to its sunken central portion is at least an interior side surface of the bottom electrode).
Regarding claim 14, Hung in view of Chung teaches: The method of claim 13, wherein layer stack (as best understood to mean “the layer stack”)(Hung 216, 218, 220, 222) is formed over the dielectric material layer (Hung 206) and the bottom electrode (Hung 208, 212) such that the layer stack comprises a first horizontal portion over the upper surface of the dielectric material layer (Hung 2XX-4, 2XX-5, fig 1A-B, 2H-M, ¶0044), a first vertical portion over the outer side surface of the bottom electrode (Hung 208B)(Hung 2XX-2, 2XX-3, fig 1A-B, 2H-M, ¶0044), a second vertical portion over the interior side surface of the bottom electrode (Hung as modified to include Chung G, Hung 2XX-1, ¶0032-0044, “conformal and thin”, the layers being conformal to 208A and 212A as modified to have a recessed central portion, by definition, must at least have a vertical component to conform to G, therefore meeting a BRI), and a second horizontal portion over the central portion of the bottom electrode (Hung as modified to include Chung G, Hung 2XX-1, ¶0032-0044, “conformal and thin”, the layers being conformal to 208A and 212A as modified to have a recessed central portion, by definition, must have at least a horizontal surface above Chung F which has no vertical component and therefore must be horizontal)(Hung as modified to include Chung, Hung 118-126, fig 1A-B, 2H-M, ¶0032-0044, Chung fig 3F).
Regarding claim 15, Hung in view of Chung teaches: The method of claim 14, wherein an angle between the first horizontal portion (Hung 2XX-4, 2XX-5) and the first vertical portion (Hung 2XX-2, 2XX-3) of the layer stack is less than 90° (Hung ¶0031, layers are formed “conformal and thin” having profile 215 which includes an acute angle between portions of 206B, 2XX-4 and 2XX-2, and between portions of 208B, 2XX-5 and 2XX-3) and an angle between the second horizontal portion (Hung as modified to include Chung G, Hung 2XX-1, portions above F) and the second vertical portion (Hung as modified to include Chung G, Hung 2XX-1, portions in G) of the layer stack is greater than 90° (Chung fig 3E, at least the outside angle forming F must be greater than 90°).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US 20200227634 A1, hereafter Hung) in view of Chung et al (US 20100019218 A1, hereafter Chung), as applied to claim 10 above, and further in view of Ando et al (US 20190165269 A1, hereafter Ando).
Regarding claim 11, Hung in view of Chung teaches: The method of claim 10.
Hung in view of Chung does not explicitly teach: wherein recessing the upper surface of the dielectric material layer relative to the upper surface of the bottom electrode comprises etching the dielectric material layer and the bottom electrode using an etch chemistry that has a higher etch selectivity for the dielectric material layer relative to the first conductive material and the second conductive material.
Ando, in the same field of endeavor of semiconductor device manufacturing, teaches: recessing an upper surface of a dielectric material layer (Ando 2, ¶0042) relative to an upper surface of a bottom electrode (Ando 10, ¶0042)(Ando fig 4, 5, ¶0042-0043) comprises etching the dielectric material layer and the bottom electrode using an etch chemistry that has a higher etch selectivity for the dielectric material layer relative to the bottom electrode (Ando ¶0042, “etchant of the etch process may be selected to remove the material of the first dielectric layer 2 without etching, i.e., removing, the material of the lower electrode 10”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the recessing method of the upper surface of the dielectric material layer relative to the upper surface of the bottom electrode of Hung in view of Chung such that “etching the dielectric material layer and the bottom electrode using an etch chemistry that has a higher etch selectivity for the dielectric material layer relative to the first conductive material and the second conductive material”, as taught by Ando, in order to eliminate the need for a patterning mask to recess the dielectric material layer and/or in order to provide for corners on the bottom electrode, thereby lowering the forming voltage of the device and/or reducing device variability (Ando ¶0016, 0042).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US 20200227634 A1, hereafter Hung) in view of Chung et al (US 20100019218 A1, hereafter Chung) and Ando et al (US 20190165269 A1, hereafter Ando), as applied to claim 11 above, and further in view of Hsueh et al (US 20210287994 A1, hereafter Hsueh).
Regarding claim 12, Hung in view of Chung and Ando teaches: The method of claim 11.
Hung in view of Chung and Ando does not explicitly teach: wherein recessing the central portion of the bottom electrode relative to an outer portion of the bottom electrode (as best understood to mean “the outer portion of the bottom electrode”) comprises etching the bottom electrode using an etch chemistry having a higher etch selectivity for the second conductive material relative to the first conductive material.
Hsueh, in the same field of endeavor of semiconductor device manufacturing, teaches: recessing a central portion of a bottom electrode (Hsueh 106) comprising a second conductive material (Hsueh 110) relative to an outer portion of the bottom electrode comprising a first conductive material (Hsueh 108)(Hsueh fig 17, ¶0067), comprises etching the bottom electrode using an etch chemistry having a higher etch selectivity for the second conductive material relative to the first conductive material (Hsueh ¶0067, fig 17).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify recessing the central portion of the bottom electrode relative to the outer portion of the bottom electrode of Hung in view of Chung and Ando such that it used an “etch chemistry having a higher etch selectivity for the second conductive material relative to the first conductive material”, as taught by Hsueh, in order to form sharp peaks while maintaining a vertical height of first conductive material, thereby improving an active area of the device (Hung ¶0049, Chung ¶0022).
Further, the substitution of an etch chemistry selectivity represents a simple substitution of one known method for another to obtain predicable results. MPEP 2143(I)(B). Chung and Hsueh each etch the conductive material of plug structure in an opening of a dielectric material such that their upper surfaces are recessed below outer points (Chung ¶0027, fig 3E, Hsueh ¶0065-0067, fig 17). Additionally, Hung and Hsueh use similar liner and fill materials (Hung ¶0022, 0024, Hsueh ¶0025) such that the etch of Hsueh predictably recesses the second conductive material of Hung relative to the first conductive material. A person of ordinary skill in the art would have found it obvious to select the etch of Hsueh because Chung requires the edges of the bottom electrode to remain above the central portion to form sharp peaks (Chun ¶0022, 0027, 0029), whereas Hsueh etches the conductive body faster than the conductive liner, thereby ensure the desired geometry.
Claims 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US 20200227634 A1, hereafter Hung), as applied to claim 16 above, and further in view of Sung et al (US 20170222128 A1, hereafter Sung).
Regarding claim 17, Hung teaches: The method of claim 16, wherein forming the conductive via (Hung 234)(Hung 132) comprises:
forming a second dielectric material layer (Hung 232, ¶0047-0048) over the layer stack (Hung 216, 218, 220, 222), the bottom electrode (Hung 208, 212) and the dielectric material layer (Hung 206)(Hung 130, fig 1B, 2O, ¶0047);
forming an opening (Hung ¶0050) through the second dielectric material layer (Hung 132, fig 1B, 2P, ¶0049-0050); and
forming a conductive material (Hung 234, ¶0050) in the opening through the second dielectric material layer (Hung 132, fig 1B, 2P, ¶0049-0051).
Hung does not explicitly teach: wherein a portion of the layer stack extending over the corner portion of the bottom electrode is exposed in the opening through the second dielectric material layer.
Sung, in the same field of endeavor of semiconductor device manufacturing, teaches: forming an opening (Sung 123A, ¶0059, under a BRI of an opening) through a second dielectric material layer (Sung 125, ¶0056-0058) wherein a portion of a layer stack (Sung 132, 131, 135, 133, ¶0035, 0059) having a top surface and a side surface are exposed in the opening through the second dielectric material layer (Sung ¶0059, fig 14).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Hung such that the opening formed in the second dielectric material layer exposed a top surface and a side surface of the layer stack, as taught by Sung, and such that “a portion of the layer stack extending over the corner portion of the bottom electrode is exposed in the opening through the second dielectric material layer”, in order to expose a larger surface are between the top electrode and conductive via, thereby ensuring a sufficient contact interface and/or lowering series resistance (Sung ¶0025).
Regarding claim 19, Hung in view of Sung teaches: The method of claim 17, further comprising: forming a passivation layer (Hung 230, ¶0046, “silicon nitride”, similar to Sung 127C, ¶0038, “silicon nitride”, applicant discloses that suitable materials for a passivation layer includes “silicon nitride”, spec ¶0142) over the layer stack (Hung 216, 218, 220, 222)(Hung 128, fig 1B, ¶0045-0046), wherein the second dielectric layer (as best understood to mean “the second dielectric material layer”)(Hung 232, similar to Sung 125) is formed over the passivation layer (Hung fig 2O, ¶0047, similar to Sung fig 14).
Regarding claim 20, Hung in view of Sung teaches: The method of claim 19, wherein the passivation layer (Hung 230, similar to Sung 127C) comprises at least one of silicon nitride (SiN)(Hung ¶0046, “silicon nitride”, similar to Sung ¶0038), silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon oxycarbide (SiOC).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US 20200227634 A1, hereafter Hung) in view of Sung et al (US 20170222128 A1, hereafter Sung), as applied to claim 17 above, and further in view of Higano et al (US 20150109093 A1, as cited in the IDS dated 05/06/2026, hereafter Higano).
Regarding claim 18, Hung in view of Sung teaches: The method of claim 17.
Hung in view of Sung does not explicitly teach: wherein the conductive via contacts the layer stack vertically below the corner portion of the bottom electrode.
Higano, in the same field of endeavor of semiconductor device manufacturing, teaches: a conductive via (Higano 15, ¶0062, under a broadest reasonable interpretation (BRI) of a “via”) contacts a layer stack (Higano 13, 14, ¶0061-0062) vertically below a corner portion of a bottom electrode (Higano 11, ¶0061, corner portions of top surface of 11)(Higano fig 6C, 9B, 19C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify forming the conductive via of Hung in view of Sung such that “the conductive via contacts the layer stack vertically below the corner portion of the bottom electrode”, as taught by Higano, in order to increase the contact area between the conductive via and the top electrode, thereby reducing the resistance and the voltage to from and switch the switching layer (Higano ¶0066, 0091-0097).
Allowable Subject Matter
Claim 4 and 5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Walls et al (US 20150236257 A1) is cited as an example of an analogous method wherein a bottom electrode is etched into a concave shape prior to forming an electrolyte layer and a top electrode.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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