DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/12/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-10, 12-14 and 19-20 of U.S. Patent No. 12,100,770. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 1, Pat '770 discloses, in claims 10 and 12, a device comprising: a substrate; a first transistor on the substrate, having a first gate structure extending in a first direction; a second transistor on the substrate, having a second gate structure aligned with the first gate structure and extending in the first direction, the second gate structure electrically isolated from the first gate structure; an isolation region in the substrate and between the first transistor and the second transistor in the first direction; a gate isolation structure in contact with the first gate structure, the second gate structure, and the isolation region, the gate isolation structure comprising: a first portion extending from an upper surface of the isolation region to an upper surface of the first gate structure and an upper surface of the second gate structure; a second portion extending from the upper surface of the first portion to a height above the upper surfaces of the first and second gate structures (all limitations are the same with the limitations recited in claim 10 of Pat '770);
a third transistor having a third gate structure aligned with the first gate structure and extending in the first direction, the third gate structure electrically isolated from the first gate structure; an inactive block between the first transistor and the third transistor (all limitations are the same with the limitations recited in claim 12 of Pat '770); and
a dielectric plug extending from an upper surface of the inactive block, through an adhesive layer on the first gate structure and the second gate structure, and through a conductive layer on the adhesive layer, to at least an upper surface of the conductive layer ("a conductive layer on the adhesive layer" and “a second dielectric plug extending from an upper surface of the inactive block, through the adhesive layer and the conductive layer, to at least an upper surface of the conductive layer”, in claims 10 and 12 of Pat '770, are interpreted as the same limitation).
Regarding claim 2, Pat '770 discloses the device of claim 1 as described above.
Pat '770 does not explicitly disclose a first dielectric isolation feature on a first sidewall of the inactive block; a second dielectric isolation feature on a second sidewall of the inactive block, the second sidewall facing the first sidewall; a source/drain feature extending from the first sidewall to the second sidewall.
Pat '770 teaches, in claim 2, a first dielectric isolation feature on a first sidewall of the inactive block; a second dielectric isolation feature on a second sidewall of the inactive block, the second sidewall facing the first sidewall; a source/drain feature extending from the first sidewall to the second sidewall ("a first dielectric isolation feature on a first sidewall of the first inactive fin; a second dielectric isolation feature on a second sidewall of the second inactive fin, the second sidewall facing the first sidewall; and a source/drain feature extending from the first sidewall to the second sidewall”, in claim 2 of Pat '770, are interpreted as the same limitation), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claims 10 and 12 of Pat '770 to have the first dielectric isolation feature on a first sidewall of the inactive block; the second dielectric isolation feature on a second sidewall of the inactive block, the second sidewall facing the first sidewall; the source/drain feature extending from the first sidewall to the second sidewall, as taught by claim 2 of Pat '770, for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 3, Pat '770 discloses the device of claim 2 as described above.
Pat '770 further teaches, in claim 3, the first dielectric isolation feature comprises: a first dielectric layer having a first dielectric constant; and a liner layer between the first dielectric layer and the first sidewall of the inactive block ("the first dielectric isolation feature comprises: a first dielectric layer having a first dielectric constant; and a liner layer between the first dielectric layer and the first sidewall”, in claim 3 of Pat '770, are interpreted as the same limitation), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 4, Pat '770 discloses the device of claim 3 as described above.
Pat '770 further teaches, in claim 4, the liner layer is the same layer as, and continuous with, a gate spacer layer of the third gate structure (all limitations are the same with the limitations recited in claim 4 of Pat '770), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 5, Pat '770 discloses the device of claim 4 as described above.
Pat '770 further teaches, in claim 5, the liner layer comprises polysilicon (all limitations are the same with the limitations recited in claim 5 of Pat '770), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 6, Pat '770 discloses the device of claim 3 as described above.
Pat '770 further teaches, in claim 6, the liner layer comprises a dielectric material having a second dielectric constant lower than the first dielectric constant (all limitations are the same with the limitations recited in claim 6 of Pat '770), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 7, Pat '770 discloses the device of claim 2 as described above.
Pat '770 further teaches, in claim 7, the first dielectric isolation feature comprises: a liner layer on the first sidewall, an upper surface of an isolation structure, and a third sidewall of the source/drain feature; and a second dielectric layer laterally between vertical portions of the liner layer (all limitations are the same with the limitations recited in claim 7 of Pat '770), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 8, Pat '770 discloses the device of claim 7 as described above.
Pat '770 further teaches, in claim 8, the liner layer has a first dielectric constant; and the second dielectric layer has a second dielectric constant less than the first dielectric constant (all limitations are the same with the limitations recited in claim 8 of Pat '770), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 9, Pat '770 discloses the device of claim 2 as described above.
Pat '770 further teaches, in claim 9, the liner layer has a first dielectric constant; and the second dielectric layer has a second dielectric constant less than the first dielectric constant (all limitations are the same with the limitations recited in claim 9 of Pat '770), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 10, Pat '770 discloses the device of claim 1 as described above.
Pat '770 further discloses, in claim 13, a dielectric capping layer overlying the first and second gate structures; wherein the second portion extends through the dielectric capping layer, and an upper surface of the second portion is substantially coplanar with an upper surface of the dielectric capping layer (all limitations are the same with the limitations recited in claim 13 of Pat '770).
Regarding claim 11, Pat '770 discloses, in claims 10 and 13, a device comprising: a substrate; a first transistor on the substrate, having a first gate structure extending in a first direction; a second transistor on the substrate, having a second gate structure aligned with the first gate structure and extending in the first direction, the second gate structure electrically isolated from the first gate structure; an isolation region in the substrate and between the first transistor and the second transistor in the first direction; a gate isolation structure in contact with the first gate structure, the second gate structure, and the isolation region, the gate isolation structure comprising: a first portion extending from an upper surface of the isolation region to an upper surface of the first gate structure and an upper surface of the second gate structure; a second portion extending from the upper surface of the first portion to a height above the upper surfaces of the first and second gate structures (all limitations are the same with the limitations recited in claim 10 of Pat '770); and
a dielectric capping layer overlying the first and second gate structures; wherein the second portion extends through the dielectric capping layer, and an upper surface of the second portion is substantially coplanar with an upper surface of the dielectric capping layer (all limitations are the same with the limitations recited in claim 13 of Pat '770).
Regarding claim 12, Pat '770 discloses the device of claim 11 as described above.
Pat '770 further discloses, in claim 10, an adhesive layer on the first gate structure and the second gate structure, wherein the adhesive layer comprises a metal nitride; and a conductive layer on the adhesive layer, wherein the conductive layer comprises fluorine-free tungsten (all limitations are the same with the limitations recited in claim 10 of Pat '770).
Regarding claim 13, Pat '770 discloses the device of claim 11 as described above.
Pat '770 further discloses, in claims 10 and 12, a third transistor having a third gate structure aligned with the first gate structure and extending in the first direction, the third gate structure electrically isolated from the first gate structure; an inactive block between the first transistor and the third transistor (all limitations are the same with the limitations recited in claim 12 of Pat '770); and a dielectric plug extending from an upper surface of the inactive block, through an adhesive layer on the first gate structure and the second gate structure, and through a conductive layer on the adhesive layer, to at least an upper surface of the conductive layer ("a conductive layer on the adhesive layer" and “a second dielectric plug extending from an upper surface of the inactive block, through the adhesive layer and the conductive layer, to at least an upper surface of the conductive layer”, in claims 10 and 12 of Pat '770, are interpreted as the same limitation).
Regarding claim 14, Pat '770 discloses the device of claim 13 as described above.
Pat '770 does not explicitly disclose a first dielectric isolation feature on a first sidewall of the inactive block; a second dielectric isolation feature on a second sidewall of the inactive block, the second sidewall facing the first sidewall; a source/drain feature extending from the first sidewall to the second sidewall.
Pat '770 teaches, in claim 2, a first dielectric isolation feature on a first sidewall of the inactive block; a second dielectric isolation feature on a second sidewall of the inactive block, the second sidewall facing the first sidewall; a source/drain feature extending from the first sidewall to the second sidewall ("a first dielectric isolation feature on a first sidewall of the first inactive fin; a second dielectric isolation feature on a second sidewall of the second inactive fin, the second sidewall facing the first sidewall; and a source/drain feature extending from the first sidewall to the second sidewall”, in claim 2 of Pat '770, are interpreted as the same limitation), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claims 10 and 12 of Pat '770 to have the first dielectric isolation feature on a first sidewall of the inactive block; the second dielectric isolation feature on a second sidewall of the inactive block, the second sidewall facing the first sidewall; the source/drain feature extending from the first sidewall to the second sidewall, as taught by claim 2 of Pat '770, for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 15, Pat '770 discloses the device of claim 14 as described above.
Pat '770 further teaches, in claim 3, the first dielectric isolation feature comprises: a first dielectric layer having a first dielectric constant; and a liner layer between the first dielectric layer and the first sidewall of the inactive block ("the first dielectric isolation feature comprises: a first dielectric layer having a first dielectric constant; and a liner layer between the first dielectric layer and the first sidewall”, in claim 3 of Pat '770, are interpreted as the same limitation), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 16, Pat '770 discloses the device of claim 15 as described above.
Pat '770 further teaches, in claim 4, the liner layer is the same layer as, and continuous with, a gate spacer layer of the third gate structure (all limitations are the same with the limitations recited in claim 4 of Pat '770), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 17, Pat '770 discloses the device of claim 16 as described above.
Pat '770 further teaches, in claim 5, the liner layer comprises polysilicon (all limitations are the same with the limitations recited in claim 5 of Pat '770), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 18, Pat '770 discloses the device of claim 15 as described above.
Pat '770 further teaches, in claim 6, the liner layer comprises a dielectric material having a second dielectric constant lower than the first dielectric constant (all limitations are the same with the limitations recited in claim 6 of Pat '770), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 19, Pat '770 discloses the device of claim 14 as described above.
Pat '770 further teaches, in claim 7, the first dielectric isolation feature comprises: a liner layer on the first sidewall, an upper surface of an isolation structure, and a third sidewall of the source/drain feature; and a second dielectric layer laterally between vertical portions of the liner layer (all limitations are the same with the limitations recited in claim 7 of Pat '770), for the purpose of providing gate isolation structures to improve spacing constraints by employing a self- aligned fabrication process.
Regarding claim 20, Pat '770 discloses, in claims 14, 19, and 20, a method, comprising: forming a first fin stack and a second fin stack; forming an inactive fin in a first opening between the first fin stack and the second fin stack by a self-aligned process; forming a first gate structure over the first fin stack, and a second gate structure over the second fin stack, wherein the first gate structure is isolated from the second gate structure by the inactive fin; forming a dielectric plug over the inactive fin after forming the first and second gate structures; forming a bridge conductor layer on the first and second gate structures, wherein a the bridge conductor layer extends to a vertical height that is below an upper surface of the dielectric plug (all limitations are the same with the limitations recited in claim 14 of Pat '770);
forming an adhesive layer on the first gate structure and the second gate structure extending to substantially the vertical height (all limitations are the same with the limitations recited in claim 19 of Pat '770); and electrically connecting the first gate structure to a third gate structure by the bridge conductor layer (all limitations are the same with the limitations recited in claim 20 of Pat '770); wherein the bridge conductor layer is formed using the adhesive layer as a seed layer in a selective deposition process (all limitations are the same with the limitations recited in claim 19 of Pat '770).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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