DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Reznicek et al. (US Pub. 2020/0044023; hereinafter “Reznicek-023”).
Regarding Claim 8, Reznicek-023 discloses a semiconductor structure, comprising: a plurality of nanostructures 14NS (page 4, paragraph 41) over a substrate 10 (see fig. 13); a gate structure (34, 36) having a first portion wrapping around each of the plurality of nanostructures 14NS (page 7, paragraph 68) and a second portion on a topmost nanostructure 14NS of the plurality of nanostructures 14NS (see fig. 13); a source/drain feature 26 (page 6, paragraph 58) coupled to the plurality of nanostructures 14NS (see fig. 13); and an air gap 28 (page 6, paragraph 62) disposed vertically between the source/drain feature 26 and the substrate 10, wherein a portion of substrate 10 is exposed to the air gap 28 (see fig. 13) (Note that the nanostructure channels are designated as “14NS” based on page 4, paragraph 41, and Figure 11. However, in Figure 13, they are mistakenly labeled as “12NS”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek (US Pat. 10,170,638; hereinafter “Reznicek-638”) in view of Song et al. (US Pub. 2020/0381547; hereinafter “Song”).
Regarding Claim 1, Reznicek-638 discloses a semiconductor device, comprising: a base fin 10 (FinFET; col. 1, lines 16-19) having a channel region (a region where a gate structure is formed) and a source/drain region (a region where a source/drain is formed) (see fig. 8); a plurality of nanostructures 14P (col. 7, lines 6-25) over the channel region (see fig. 8); a gate structure (32, 34) over a substrate 10 and wrapping around each of the plurality of nanostructures 14P (col. 10, lines 2-9); a bottom isolation layer (22, 20L) (col. 8, lines 3-12) disposed over the source/drain region and extending into the base fin 10 (see fig. 8); a source/drain feature 26 (col. 8, lines 31-35) disposed over the bottom isolation layer (22, 20L) and interfacing sidewalls of the plurality of nanostructures 14P (see fig. 8); a gap 24 (col. 8, lines 41-45) between the bottom isolation layer (22, 20L) and the source/drain feature 26 (see fig. 8); a gate spacer 20S (col. 8, lines 22-26) disposed along a sidewall of the gate structure (32, 34) over the plurality of nanostructures 14P (see fig. 8); a first dielectric layer 30 (col. 9, lines 18-24) over the source/drain feature 26 (see fig. 8), wherein top surfaces of the first dielectric layer 30 and the gate spacer 20S are coplanar (see fig. 8).
Reznicek-638 fails to disclose explicitly a second dielectric layer over and interfacing the gate spacer and the first dielectric layer.
However, Song discloses an upper insulation layer 162 (page 5, paragraph 53) over and interfacing a spacer structure 130 (page 4, paragraph 42) and an inter-gate insulation layer 154 (page 5, paragraph 53) (see fig. 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a second dielectric layer over a first dielectric layer, as taught by Song, to obtain a contact plug passing through the dielectric layers providing electrical connection between a source/drain region and a wiring structure while protecting the gate structure.
Regarding Claim 2, Reznicek-638 fails to disclose explicitly a source/drain contact extending through the first dielectric layer and the second dielectric layer and electrically coupled to the source/drain feature.
However, Song discloses a contact plug 166 extending through an inter-gate insulation layer 154 and an upper insulation layer 162 and electrically coupled to a source/drain region 140 (page 5, paragraph 53; see fig. 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a contact plug, as taught by Song, to obtain an electrical connection between the source/drain region and a wiring structure.
Regarding Claim 6, Reznicek-638 discloses wherein a bottom surface of the gate structure (32, 34) is above a top surface of the bottom isolation layer (22, 20L) (see fig. 8).
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek-023 in view of Song.
Regarding Claim 15, Reznicek-023 discloses further comprising: a dielectric layer 31 (page 7, paragraph 66) adjacent to the gate structure (34, 36) and extending over an entirety of a top surface of the source/drain feature 26 (see fig. 13).
Reznicek-023 fails to disclose explicitly a source/drain contact extending through the dielectric layer to couple to the source/drain feature.
However, Song discloses a contact plug 166 extending through an inter-gate insulation layer 154 and an upper insulation layer 162 and electrically coupled to a source/drain region 140 (page 5, paragraph 53; see fig. 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a contact plug, as taught by Song, to obtain an electrical connection between the source/drain region and a wiring structure.
Allowable Subject Matter
Claims 3-5, 7 and 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 recites a gate via extending through the second dielectric layer and electrically coupled to the gate structure, wherein top surfaces of the gate via and the source/drain contact are coplanar.
Claim 4 recites the gap exposes a portion of the substrate.
Claim 5 recites the bottom isolation layer comprises aluminum oxide.
Claim 7 recites a height difference between the bottom surface of the gate structure and the top surface of the bottom isolation layer is in a range between about 1 nm and about 2 nm.
Claim 9 recites an isolation layer on the substrate, wherein the air gap exposes an entirety of a top surface of the isolation layer.
Claim 14 recites a plurality of gaps disposed between the source/drain feature and the plurality of inner spacer features, respectively.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claims 10-13 depend from claim 9, so they are objected for the same reason.
Claims 16-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 16 recites a first air gap disposed between and exposing both the source/drain feature and a topmost inner spacer feature of the plurality of inner spacer features.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 17-20 depend from claim 16, so they are allowed for the same reason.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 8, 14 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5 of U.S. Patent No. 11,854,896 (hereinafter “Pat-896”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-896 discloses all the claimed limitations. See rejections below.
Regarding Claim 8, Pat-896 discloses a semiconductor structure, comprising: a plurality of nanostructures (first and second semiconductor stacks including first and second semiconductor layers; see claim 1) over a substrate (see claim 1); a gate structure having a first portion wrapping around each of the plurality of nanostructures (see claim 1) and a second portion on a topmost nanostructure of the plurality of nanostructures (because the metal gate structure wrapping each of the first and second semiconductor layers, the metal gate structure necessarily extends over and includes a portion disposed on the topmost semiconductor layer of the plurality of first and second semiconductor layers); a source/drain feature coupled to the plurality of nanostructures (a bulk S/D feature between the first semiconductor stack and the second semiconductor stack; see claim 1); and an air gap disposed vertically between the source/drain feature and the substrate (the bulk S/D feature is separated from the substrate by a first air gap; see claim 1), wherein a portion of substrate is exposed to the air gap (because the isolation layer covers only a portion of the substrate below the bulk S/D feature, at least another portion of the substrate remains uncovered by the isolation layer and is therefore exposed to the first air gap; see claim 1).
Regarding Claim 14, Pat-896 discloses further comprising: a plurality of inner spacer features disposed between the source/drain feature and the gate structure (inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; see claim 1); and a plurality of gaps disposed between the source/drain feature and the plurality of inner spacer features, respectively (the bulk S/D feature is separated from the inner spacers by second air gaps; see claim 1).
Regarding Claim 15, Pat-896 discloses further comprising: a dielectric layer adjacent to the gate structure and extending over an entirety of a top surface of the source/drain feature (a first dielectric layer disposed over the bulk S/D feature and sandwiched between the first gate spacer and the second gate spacer; see claim 1); and a source/drain contact extending through the dielectric layer to couple to the source/drain feature (see claim 5).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 September 17, 2026
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