DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/25/2024 was filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7, 9-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,266,715, herein after ‘715. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of ‘715 recites claimed limitations of present claims 1-7, 9-20.
Regarding claim 1, Claims 1, 3 and 13 or claim 15 of ‘715 disclose:
A semiconductor device, comprising:
a substrate,
a dielectric isolation structure disposed on the substrate,
a semiconductor fin disposed on the substrate,
a dummy fin disposed on the substrate and parallel to the semiconductor fin, and
a conducting gate disposed over the fin and the dummy fin (lines 35-50, Col. 12),
wherein the dummy fin includes at least a first sublayer and a second sublayer over the first sublayer (claim 3; lines 53-57, Col. 12), and
wherein the first sublayer extends into the dielectric isolation structure (lines 8-11, Col. 14; or claim 15 disclosed a bottom portion of the dummy fin embedded into the dielectric isolation structure).
Regarding claim 2, Claim 1 of ‘715 discloses wherein a portion of the first sublayer extended into the dielectric isolation structure has a rounded profile (lines 49-50, Col. 12).
Regarding claim 3, Claims 1 and 3 of ‘715 disclose the founded profile of the dummy fin but doesn’t mention that it has a depth of 100 nm or less. However, the selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 4, Claim 4 of ‘715 discloses wherein the dielectric isolation structure includes a shallow trench isolation structure (lines 59-61, Col. 12).
Regarding claim 5, Claim 3 of ‘715 discloses wherein the dummy fin further includes a third sublayer disposed over a top surface of each of the first sublayer and the second sublayer (lines 53-58, Col. 12).
Regarding claim 6, Claim 12 of ‘715 discloses wherein the third sublayer includes a first slanted bottom surface and a second slanted bottom surface that converge at a point (lines 30-32, Col. 13: V-shape).
Regarding claim 7, Claim 13 of ‘715 discloses wherein the third sublayer includes a bottom surface that extends horizontally across the top surface of each of the first sublayer and the second sublayer (lines 32-35, Col. 13).
Regarding claim 9, Claims 15, and 18 of ‘715 disclose:
A semiconductor device, comprising:
a substrate,
a dielectric isolation structure disposed on the substrate,
a semiconductor fin protruding from the substrate,
a dummy fin protruding from the substrate and extending parallel to the semiconductor fin, and
a gate disposed over the fin and the dummy fin,
wherein the dummy fin has a multilayer structure, and
wherein a bottom surface of the dummy fin is disposed between a top surface and a bottom surface of the dielectric isolation structure along a vertical direction (lines 3-17, 22-25, Col. 14).
Regarding claim 10, Claim 15 of ‘715 discloses:
Wherein a sidewall of the fin is in direct contact with the isolation structure, and wherein a sidewall of the dummy fin is free of contact with the dielectric isolation structure (fin protrudes from substrate and dummy fin protrudes from isolation).
Regarding claim 11, Claim 15 of ‘715 discloses: wherein a top surface of the dummy fin is above a top surface of the semiconductor fin (lines 3-17, Col. 14).
Regarding claim 12, Claim 15 of ‘715 discloses:
Wherein the bottom surface of the dummy fin has a rounded profile (lines 3-17, Col. 14).
Regarding claim 13, Claim 18 of ‘715 discloses: wherein the dummy fin includes a first sublayer, a second sublayer over the first sublayer, and a third sublayer over the second sublayer (lines 22-26, Col. 14).
Regarding claim 15, Claim 19 of ‘715 disclose:
wherein a bottom surface of the third sublayer has a pointed profile towards the substrate (lines 28-30, V-shape, Col. 14).
Regarding claim 16, Claim 13 of ‘715 disclose:
Wherein a bottom surface of the third sublayer extends along a horizontal plane (lines 32-35, Col. 13).
Regarding claim 17, Claim 10 of ‘715 disclose:
Wherein the first sublayer and the second sublayer have different compositions (lines 23-25, Col. 13).
Regarding claim 18, Claims 15, and 18 of ‘715 disclose:
A semiconductor device, comprising:
a substrate,
a dielectric isolation structure disposed on the substrate,
a semiconductor fin protruding from the substrate,
a dummy fin protruding from the substrate and extending parallel to the semiconductor fin, and
an active gate disposed over the fin and the dummy fin,
wherein the dummy fin has a multilayer structure, and
wherein a bottom surface of the dummy fin is embedded in the isolation structure
(lines 3-17, 22-25, Col. 14).
Regarding claim 19, Claim 15 of ‘715 disclose:
Wherein a top surface of the active gate is above a top surface of the dummy fin (lines 14-16, Col. 14).
Regarding claim 20, Claim 19 of ‘715 disclose:
Wherein the dummy fin includes a first sublayer, a second sublayer over the first sublayer, and a third sublayer over the second sublayer, and wherein a bottom surface of the third sublayer has a pointed profile towards the substrate (lines 28-30, Col. 14).
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,266,715 in view of 2021/0242206.
Regarding claim 8, Claim 1 of ‘715 fails to disclose wherein the first sublayer surrounded and directly contacts a bottom and sidewall surfaces of the second sublayer.
Lin discloses the first sublayer surrounding and directly contact a bottom and sidewall surfaces of the second sublayer (claim 17 of Lin ‘206).
It would have been obvious to one having ordinary skill in the art at the time invention was made to modify ‘715 in view of ‘206 in order to provide the known multilayer dummy fin configuration and facilitate control of the dummy fin gap-fill process.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 8, 9-11, 13, 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al., U.S. Pub. No. 2020/0118867.
Regarding claim 1, Lin ‘8867 discloses:
A semiconductor device, comprising:
a substrate 5 ([0017]-[0019]),
a dielectric isolation structure 64 ([0027]) disposed on the substrate,
a semiconductor fin 52 ([0017], [0021]) disposed on the substrate,
a dummy fin 62 disposed on the substrate and parallel to the semiconductor fin [0027], and
a conducting gate 68/72 disposed over the fin 52 and the dummy fin 62 ([0036]-[0039]),
wherein the dummy fin includes at least a first sublayer 58 and a second sublayer 60 over the first sublayer, and
wherein the first sublayer 58 extends into the dielectric isolation structure 64 ([0027] expressly teaches that the upper portion of dielectric line 58 forms dummy fin 62 while the lower portion of dielectric liner 58 forms part of isolation region 64).
Regarding claim 4, Lin ‘8867 discloses wherein the dielectric isolation structure 64 includes a shallow trench isolation structure [0027].
Regarding claim 5, Lin ‘8867 discloses wherein the dummy fin further includes a third sublayer disposed over a top surface of each of the first sublayer and the second sublayer (layers 56/58/60).
Regarding claim 8, Lin ‘8867 discloses wherein the first sublayer surrounded and directly contact a bottom and sidewall surfaces of the second sublayer (the conformal liner 56 along the underlying surfaces [0023], liner 58 over liner 56 [0024], material 60 over films 56/58 [0025])).
Regarding claim 9, Lin ‘8867 discloses:
A semiconductor device, comprising:
a substrate 50 [0019],
a dielectric isolation structure 64 disposed on the substrate [0027], Fig. 8,
a semiconductor fin 52 protruding from the substrate [0021], [0027], Fig. 8,
a dummy fin 62 protruding from the substrate and extending parallel to the semiconductor fin [0027], and
a gate 68/72 disposed over the fin and the dummy fin,
wherein the dummy fin 62 has a multilayer structure 58, 60, and
wherein a bottom surface of the dummy fin 62 is disposed between a top surface and a bottom surface of the dielectric isolation structure 64 along a vertical direction [0036], [0039].
Regarding claim 10, Lin ‘8867 discloses:
Wherein a sidewall of the fin 52 is in direct contact with the isolation structure 64, and wherein a sidewall of the dummy fin 62 is free of contact with the dielectric isolation structure (Fig. 8, [0027]).
Regarding claim 11, Lin ‘8867 discloses: wherein a top surface of the dummy fin 62 is above a top surface of the semiconductor fin 52 (Fig. 8, [0027]).
Regarding claim 13, Lin ‘8867 discloses: wherein the dummy fin includes a first sublayer 56, a second sublayer 58 over the first sublayer, and a third sublayer 60 over the second sublayer ([0023]-[0025]).
Regarding claim 16, Lin ‘8867 discloses:
Wherein a bottom surface of the third sublayer 60 extends along a horizontal plane (Fig. 8, [0025]).
Regarding claim 17, Lin ‘8867 discloses:
Wherein the first sublayer 56 and the second sublayer 58 have different compositions ([0023]-[0024]).
Regarding claim 18, Lin ‘8867 discloses:
A semiconductor device, comprising:
a substrate 50,
a dielectric isolation structure 64 disposed on the substrate,
a semiconductor fin 52 protruding from the substrate,
a dummy fin 62 protruding from the substrate and extending parallel to the semiconductor fin, and
an active gate 68/72 disposed over the fin and the dummy fin,
wherein the dummy fin has a multilayer structure 58+60, and
wherein a bottom surface of the dummy fin is embedded in the isolation structure (bottom portion of dummy fin 62 embedded in isolation structure 64, Fig. 8, [0027]).
Regarding claim 19, Lin ‘8867 discloses:
Wherein a top surface of the active gate 68/72 is above a top surface of the dummy fin 62 (Figs. 1-8).
Regarding claim 20, Lin ‘8867 discloses:
Wherein the dummy fin 62 includes a first sublayer, a second sublayer over the first sublayer, and a third sublayer over the second sublayer, and wherein a bottom surface of the third sublayer has a pointed profile towards the substrate [0027].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/THAO P LE/Primary Examiner, Art Unit 2818
Prosecution Insights