Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-12, 14-18 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cheng et al. (US Pat. Pub. 2021/0305090).
Regarding claim 1, Cheng teaches a method of fabricating a semiconductor structure, comprising:
forming a recess in a metal layer adjacent a dielectric layer [fig. 4, metal layer 32 is recessed adjacent dielectric layer 24a];
forming an etch stop layer over the metal layer, within the recess, and over the dielectric layer [fig. 6, etch stop 38 over 24a, 32 and in the recess] ;
removing a portion of the etch stop layer formed within the recess [fig. 11, etch stop within the recess has been removed]; and
forming a conductive via within the recess [fig. 12, 32’].
Regarding claim 2, Cheng discloses the method of claim 1, wherein the dielectric layer comprises a first dielectric layer, the method further comprising:
forming a second dielectric layer over the etch stop layer before removing the portion of the etch stop layer [fig. 8, 34 formed above 38]; and
removing a portion of the second dielectric layer before removing the portion of the etch stop layer [fig. 10, 34 is removed before 38 is removed from the recess].
Regarding claim 3, Cheng teaches the method of claim 2, wherein removing the portion of the second dielectric comprises removing the portion of the second dielectric layer using a dual damascene process [paragraph [0042], 24b is removed when 24c is patterned using dual damascene processing].
Regarding claim 4, Cheng discloses the method of claim 1, wherein forming the etch stop layer comprises forming a layer of aluminum oxide over the metal layer, within the recess and over the dielectric layer [paragraph [0037] teaches aluminum oxide for etch stop layer 38].
Regarding claim 5, Cheng teaches the method of claim 1, wherein removing the portion of the etch stop layer comprises removing the portion of the etch stop layer using wet etching processes [paragraph [0046]].
Regarding claim 6, Cheng discloses the method of claim 1, wherein the metal layer comprises a first metal layer, the method further comprising a second metal layer adjacent the conductive via [fig. 12, 30’, paragraph [0033] teaches 30 is cobalt or ruthenium].
Regarding claim 7, Cheng teaches the method of claim 1, further comprising planarizing a top surface of the metal layer before forming the recess in the metal layer [fig. 2 and 3, 32 is planarized, paragraph [0034]].
Regarding claim 8, Cheng discloses a method of fabricating a semiconductor structure, comprising:
forming a first metal layer adjacent to a first dielectric layer [fig. 3, metal layer 32 adjacent dielectric 24a];
recessing the first metal layer to form a first trench [fig. 4, 32 is recessed to form trench 34];
forming an etch stop layer over the first trench and the first dielectric layer [fig. 6, etch stop 38 formed over 24a and 32];
forming a second dielectric layer over the etch stop layer to fill the first trench [fig. 8, 24b];
patterning the second dielectric layer to form a second trench, thereby exposing a portion of the etch stop layer [fig. 10, 24b is removed exposing 38];
removing the exposed portion of the etch stop layer to expose the first metal layer in the first trench [fig. 11, 38 is removed and 32 is exposed]; and
forming a second metal layer over the exposed first metal layer to form a via electrically coupled to the first metal layer [fig. 12, 32’ formed coupled to 32].
Regarding claim 9, Cheng discloses the method of claim 8, wherein forming the first metal layer includes:
patterning the first dielectric layer to form a third trench, forming the first metal layer over the patterned first dielectric layer, thereby filling the third trench, and planarizing the first metal layer such that the first metal layer is planar with and adjacent to the first dielectric layer [figs. 1-3, 24a is patterned to form trenches 26, 32 fills the trenches, 32 is planarized].
Regarding claim 10, Cheng teaches the method of claim 8, further comprising providing a contact feature electrically connected to a bottom surface of the first metal layer [paragraph [0033] devices formed on the substrate have wiring connected to 32].
Regarding claim 11, Cheng discloses the method of claim 8, wherein forming the etch stop layer includes conformally depositing an aluminum oxide layer [paragraph [0037] teaches aluminum oxide for etch stop layer 38].
Regarding claim 12, Cheng teaches the method of claim 11, wherein removing the exposed portion of the etch stop layer includes performing a wet etching process [paragraph [0046]].
Regarding claim 14, Cheng discloses the method of claim 8, wherein removing the exposed portion of the etch stop layer exposes a top surface of the first dielectric layer such that the second metal layer directly contacts the top surface of the first dielectric layer [fig. 11 and 12, a top surface of 24a is exposed at a corner, the second metal layer can be interpreted as 28’, 30’ and 32’ which directly contacts the exposed 24a corner].
Regarding claim 15, Cheng teaches the method of claim 8, wherein forming the second metal layer fills the first trench such that a bottom portion of the via directly contacts a sidewall of the first dielectric layer [figs. 11 and 12, 24a is exposed during the etch stop layer removal, the second metal layer which creates the via can be interpreted as 28’, 30’ and 32’ which directly contacts a sidewall of 24a].
Regarding claim 16, Cheng discloses a method of fabricating a semiconductor structure, comprising:
forming a first metal layer adjacent to a first dielectric layer, the first metal layer having a top surface below a top surface of the first dielectric layer [fig. 4, 32 with top surface below dielectric 24a];
depositing an etch stop layer over the first metal layer and the first dielectric layer [fig. 6, etch stop 38];
forming a second dielectric layer over the etch stop layer [fig. 8, 24b];
patterning the second dielectric layer to form a trench, the trench exposing sidewalls of the etch stop layer [fig 10, 24b is removed, sidewalls of 38 are exposed];
removing the exposed portion of the etch stop layer to expose the first metal layer [fig. 11, exposed 38 is removed, exposing 32]; and
forming a second metal layer over the exposed first metal layer to form a via electrically coupled to the first metal layer [fig. 12, 32’].
Regarding claim 17, Cheng discloses the method of claim 16, wherein forming the first metal layer includes:
patterning the first dielectric layer to form a second trench, forming the first metal layer over the patterned first dielectric layer, thereby filling the second trench, and planarizing the first metal layer such that the first metal layer is planar with and adjacent to the first dielectric layer, recessing the planarized first metal layer [figs. 1-4, 24a is patterned to form trenches 26, 32 fills the trenches, 32 is planarized, the planarized layer is recessed with trenches 34].
Regarding claim 18, Cheng teaches the method of claim 16, wherein removing the exposed portion of the etch stop layer exposes the top surface of the first dielectric layer [fig. 11, a top surface of 24a is exposed].
Regarding claim 20, Cheng discloses the method of claim 16, wherein the etch stop layer and the second dielectric layer have different compositions, and wherein the etch stop layer includes aluminum oxide [paragraph [0038] teaches 24b is ultra low-k dielectric, paragraph [0037] teaches etch stop is aluminum oxide].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claims 1-12, 14-18 and 20 above, and further in view of the following arguments.
Regarding claim 13, Cheng teaches a wet etching process but does not teach both a wet and dry etching process for recessing the first metal layer. However, when forming additional recesses by etching steps Cheng teaches using both wet and dry processes [paragraph [0030], dry etch and wet cleaning step]. It would be well known in the art to utilize multiple etching steps including a dry etch with wet clean to form a recess.
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings what is well known into the method of Cheng by forming the recess in the metal layer by both a wet and dry etching process. The ordinary artisan would have been motivated to modify Cheng in the manner set forth above for at least the purpose of utilizing a known process to ensure successful recess fabrication, additionally a wet clean after a masking and dry etch would ensure a clean surface for further processing.
Regarding claim 19, while Cheng teaches devices formed on the substrate surface and wiring connected to said devices to put them in contact with the metal layer [paragraph [0033] devices formed on the substrate have wiring connected to 32], they fail to specifically teach a source, drain or gate contact. However, it is well known in the art to use device wiring to contact sources drains and gates of transistor devices present on substrates.
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of what is well known into the method of Cheng by connecting the first metal layer to a source, drain or gate contact of a device present on the substrate. The ordinary artisan would have been motivated to modify Cheng in the manner set forth above for at least the purpose of utilizing known successful methods of connecting transistors to external signals or power using wiring.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm.
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/JOHN M PARKER/ Primary Examiner, Art Unit 2899
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