DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 09/25/2024 and 05/30/2025 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claims 1, 4, 7, and 14 are objected to because of the following informalities:
Claim 1, line 8: “passivation layer” should read --- a passivation layer ---
Claim 4, final line: “the first metal gate layer” should read --- the metal gate layer ---
Claim 7, final line: “the second metal gate layer” should read --- the metal gate layer ---
Claim 14, line 4: “the first gate all around transistor” should read --- the N-type gate all around transistor ---
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4, 8-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ando (U.S. Patent No 10,332,809) in view of Wang (U.S. PG Pub No US2019/0237336A1). * Huang (U.S. PG Pub No US2021/0134794A1) is provided as evidentiary support*
Regarding claim 1, Ando teaches an integrated circuit [see fig. 5, col 8, lines 53-67] comprising:
a plurality of first semiconductor nanosheets (14L) fig. 5 [col 9, lines 26-30] corresponding to channel regions of a P-type gate all around transistor (100) [col 8, line 56, col 9, line 26];
an interfacial dielectric layer (16L) fig. 5 [col 7, lines 1-17] (directly) on the first semiconductor nanosheets (14L);
a high-K dielectric layer (18L) fig. 5 [col 6, lines 44-50] (directly) on the interfacial dielectric layer (16L);
a metal gate layer (20L) fig. 5 [col 7, lines 34-41] (comprising titanium metal) (directly) on the high-K dielectric layer (18L) and between the first semiconductor nanosheets (14L); and
a metal gate fill material (26) fig. 5 [col 8, lines 53-67] (comprising nickel metal).
However, Ando does not explicitly disclose
a passivation layer on the metal gate layer (20L) in-situ with deposition of the metal gate layer (20L); and
a/the metal gate fill material (26) on the passivation layer.
With respect to the underline limitation(s) of “in-situ” above, they have been considered as “product by process” limitation(s) – process steps that do not yield an identifiable structure in the product. Note that a “product by process” limitation is directed to the product per se, no matter how actually made. See In re Thorpe et al. 227 USPQ 964 (CFAC, 1985) and the related case law cited therein, which makes it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935. (See MPEP 2113).
Wang teaches an integrated circuit [see fig. 11, 0018] comprising a passivation layer (20) fig. 11 [0031-0032] on (directly on) the metal gate layer (25) fig. 11 [0030] (comprising tantalum metal [0030]) with deposition of the metal gate layer (20L); and
a/the metal gate fill material (30) fig. 11 [0080-0082] on (directly on) the passivation layer (20).
With respect to layer 20 of Wang, which may be composed of titanium nitride [0030], Wang is silent with respect to “passivation” qualities of this layer. However, titanium nitride is recognized functionally as a passivation layer material in the GAA-FET prior art. For example, see [0029] of Huang (U.S. PG Pub No US2021/0134794A1) --- which discloses “the passivation layer may comprise, for example, titanium nitride, silicon, or some other suitable passivation material to further tune the work function and thus, threshold voltages of the NSFETs (102, 104, 106)” [0029 Huang].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit structure of Ando to further include the titanium nitride passivating layer [0030-0032] between the metal gate layer(s) [0030] and metal fill material(s) [0080-0082] in order to add another material to advantageously control the work function of the surrounded transistor layers [0031-0032], as taught by Wang.
Regarding claim 2, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 1. Ando in view of Wang (with reference to Wang) also teaches wherein the passivation layer (20) fig. 11 [0031-0032] is positioned between the first semiconductor nanosheets (10 in 11a) fig. 11 [0038].
Regarding claim 4, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 1. Ando also teaches further comprising:
an N-type gate all around transistor (102) [col 8, line 59, col 9, line 38] including:
a plurality of second semiconductor nanosheets (14R) fig. 5 [col 9, lines 38-53] corresponding to channel regions of the N-type gate all around transistor (102);
the interfacial dielectric layer (comprising 16R and 16L) fig. 5 [col 7, lines 1-17] (defined as collective interfacial dielectric material “16”) positioned on (supported by) the second semiconductor nanosheets;
the high-K dielectric layer (comprising 18R and 18L) fig. 5 [col 6, lines 44-50, col 7, lines 1-17] (defined as collective high-k dielectric material “18”) positioned on (supported by) the interfacial dielectric layer (16);
the metal gate layer (comprising 20L and 20R) fig. 5 [col 7, lines 34-55] (comprising titanium metal) (defined as collective metal gate material “20”) (directly) positioned directly on the high-K dielectric layer (18) (20R directly on 18R); and
the metal gate fill material (26) fig. 5 [col 8, lines 53-67] positioned on (supported by) the metal gate layer (20).
Regarding claim 8, Ando teaches an integrated circuit [see fig. 5, col 8, lines 53-67], comprising:
a plurality of first semiconductor nanosheets (14R) fig. 5 [col 9, lines 38-53] corresponding to channel regions of an N-type gate all around transistor (102) [col 8, line 59, col 9, line 38];
a plurality of second semiconductor nanosheets (14L) fig. 5 [col 9, lines 26-30] corresponding to channel regions of a P-type gate all around transistor (100) [col 8, line 56, col 9, line 26];
an interfacial dielectric layer (16R and 16L) fig. 5 [col 7, lines 1-17] (defined as collective interfacial dielectric material “16”) on (supported by) the first (14R) and second (14L) semiconductor nanosheets;
a high-K dielectric layer (18R and 18L) fig. 5 [col 6, lines 44-50, col 7, lines 1-17] (defined as collective high-k dielectric material “18”) on (supported by) the interfacial dielectric layer (16);
a first metal gate layer (20R) fig. 5 [col 7, lines 34-41] (comprising titanium metal) on (supported by) the high-K dielectric layer (18 comprising 18R) of first semiconductor nanosheets (14R);
a second metal gate layer (20L) fig. 5 [col 7, lines 34-41] (comprising titanium metal) on (supported by) the high-K dielectric layer (18 comprising 18L) of the second semiconductor nanosheets (14L).
However, Ando does not explicitly disclose
a passivation layer on the second metal gate layer (20L) formed in-situ with the second metal gate layer (20L).
With respect to the underlined limitation(s) of “in-situ” above, they have been considered as “product by process” limitation(s) – process steps that do not yield an identifiable structure in the product. Note that a “product by process” limitation is directed to the product per se, no matter how actually made. See In re Thorpe et al. 227 USPQ 964 (CFAC, 1985) and the related case law cited therein, which makes it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935. (See MPEP 2113).
Wang teaches an integrated circuit [see fig. 11, 0018] comprising a passivation layer (20) fig. 11 [0031-0032] on (directly on) the second metal gate layer (left 25) fig. 11 [0030] (comprising tantalum metal [0030]) with the second metal gate layer (left 25).
With respect to layer 20 of Wang, which may be composed of titanium nitride [0030], Wang is silent with respect to “passivation” qualities of this layer. However, titanium nitride is recognized functionally as a passivation layer material in the GAA-FET prior art. For example, see [0029] of Huang (U.S. PG Pub No US2021/0134794A1) --- which discloses “the passivation layer may comprise, for example, titanium nitride, silicon, or some other suitable passivation material to further tune the work function and thus, threshold voltages of the NSFETs (102, 104, 106)” [0029 Huang].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit structure of Ando to further include the titanium nitride passivating layer [0030-0032] between the metal gate layer(s) [0030] and metal fill material(s) [0080-0082] in order to add another material to advantageously control the work function of the surrounded transistor layers [0031-0032], as taught by Wang.
Regarding claim 9, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 8. Ando also teaches further comprising the second metal gate layer (20L) fig. 5 [col 7, lines 34-41] on (supported by) the first metal gate layer (20R) fig. 5 [col 7, lines 34-41] at the N-type gate all around transistor (102) [col 8, line 59, col 9, line 38] (through inter-supported 100/102 material).
Regarding claim 10, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 9. Ando also teaches wherein the first gate metal layer (20R) fig. 5 [col 7, lines 34-41] is not present around the second semiconductor nanosheets (14L) fig. 5 [col 9, lines 26-30].
Regarding claim 11, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 10. Ando also teaches wherein the second gate metal (20L) fig. 5 [col 7, lines 34-41] is not present around the first semiconductor nanosheets (14R) fig. 5 [col 9, lines 38-53].
Regarding claim 12, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 11. Ando also teaches further comprising a metal gate fill material (26) fig. 5 [col 8, lines 53-67] (comprising nickel metal).
Further, Ando in view of Wang (with reference to Wang) teaches further comprising a metal gate fill material (30) fig. 11 [0080] on (supported by) the passivation layer (20) fig. 11 [0031-0032] at the N-type gate all around transistor (could be 11a) fig. 11 [0024, 0038] and at the P-type gate all around transistor (could be 11b) fig. 11 [0024, 0038].
Regarding claim 13, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 12. Ando also teaches wherein the metal gate fill material (26) fig. 5 [col 8, lines 53-67] (comprising nickel metal) and the second metal gate layer (20L) fig. 5 [col 7, lines 34-41] correspond to a metal gate (are effectively gate portions of) of the P-type gate all around transistor (100) [col 8, line 56, col 9, line 26].
Regarding claim 14, Ando teaches an integrated circuit [see fig. 5, col 8, lines 53-67], comprising:
an N-type gate all around transistor (102) [col 8, line 59, col 9, line 38] including:
a plurality of first semiconductor nanosheets (14R) fig. 5 [col 9, lines 38-53] corresponding to channel regions of the N-type gate all around transistor (102);
an interfacial dielectric layer (16R and 16L) fig. 5 [col 7, lines 1-17] (defined as collective interfacial dielectric material “16”) positioned on the first semiconductor nanosheets (14R);
a high-K dielectric layer (18R and 18L) fig. 5 [col 6, lines 44-50, col 7, lines 1-17] (defined as collective high-k dielectric material “18”) positioned on (supported by) the interfacial dielectric layer (16);
a first metal gate layer (20R) fig. 5 [col 7, lines 34-41] (comprising titanium metal) on (supported by) positioned directly on the high-K dielectric layer (18 comprising 18R); and
a second metal gate layer (20L) fig. 5 [col 7, lines 34-41] positioned on (supported by inter-supported 100/102 components) the first metal gate layer (20R); and
a P-type gate all around transistor (100) [col 8, line 56, col 9, line 26] including:
a plurality of second semiconductor nanosheets (14L) fig. 5 [col 9, lines 26-30] corresponding to channel regions of the P-type gate all around transistor (100);
the interfacial dielectric layer (16) positioned on (supported by) the second semiconductor nanosheets (14L);
the high-K dielectric layer (18) positioned on (supported by) the interfacial dielectric layer (16);
the second metal gate layer (20L) fig. 5 [col 7, lines 34-41] positioned directly on the high-K dielectric layer (18 comprising 18L).
However, Ando does not explicitly disclose
an in-situ passivation layer positioned on the second metal gate layer (20L).
With respect to the underline limitation(s) of “in-situ” above, they have been considered as “product by process” limitation(s) – process steps that do not yield an identifiable structure in the product. Note that a “product by process” limitation is directed to the product per se, no matter how actually made. See In re Thorpe et al. 227 USPQ 964 (CFAC, 1985) and the related case law cited therein, which makes it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935. (See MPEP 2113).
Wang teaches an integrated circuit [see fig. 11, 0018] comprising a passivation layer (20) fig. 11 [0031-0032] positioned on (directly on) the second metal gate layer (left 25) fig. 11 [0030].
With respect to layer 20 of Wang, which may be composed of titanium nitride [0030], Wang is silent with respect to “passivation” qualities of this layer. However, titanium nitride is recognized functionally as a passivation layer material in the GAA-FET prior art. For example, see [0029] of Huang (U.S. PG Pub No US2021/0134794A1) --- which discloses “the passivation layer may comprise, for example, titanium nitride, silicon, or some other suitable passivation material to further tune the work function and thus, threshold voltages of the NSFETs (102, 104, 106)” [0029 Huang].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit structure of Ando to further include the titanium nitride passivating layer [0030-0032] between the metal gate layer(s) [0030] and metal fill material(s) [0080-0082] in order to add another material to advantageously control the work function of the surrounded transistor layers [0031-0032], as taught by Wang.
Regarding claim 15, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 14. Ando also teaches wherein the second metal gate layer (20L) fig. 5 [col 7, lines 34-41] is positioned between the second semiconductor nanosheets (14L) fig. 5 [col 9, lines 26-30].
Regarding claim 18, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 17. Ando in view of Wang (with reference to Wang) also teaches wherein the passivation layer (20) fig. 11 [0031-0032] includes a different material than the second metal gate layer (25) fig. 11 [0030] (could be formed of distinct nitride materials with different etch selectivity [0030] – i.e, 20 could be TiN and 25 could be TaN [0030], comprising different metal elements).
Regarding claim 19, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 14. Ando in view of Wang (with reference to Wang) also teaches further comprising a gate fill material (30) fig. 11 [0080] on (directly on) the passivation layer (20) fig. 11 [0031-0032].
Further, Ando in view of Wang (with reference to Wang) teaches further comprising a metal gate fill material on (supported by) the passivation layer at the N-type gate all around transistor (could be 11a) fig. 11 [0024, 0038] and at the P-type gate all around transistor (could be 11b) fig. 11 [0024, 0038].
Regarding claim 20, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 14. Ando in view of Wang (with reference to Wang) also teaches wherein the passivation layer (20) fig. 11 [0031-0032] is positioned between the second semiconductor nanosheets (10 of 11a) fig. 11 [0024, 0038], wherein the passivation layer (20) is not positioned between the first semiconductor nanosheets (10 of 11b) fig. 11 [0024, 0038].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ando (U.S. Patent No 10,332,809) in view of Wang (U.S. PG Pub No US2019/0237336A1) modified by Wang (U.S. PG Pub No US2019/0237336A1), as applied in claim 1 above, and further in view of Zang (U.S. PG Pub No US2019/0035791A1).
Regarding claim 3, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 1. However, Ando does not explicitly disclose wherein a work function of the P-type gate all around transistor (100) [col 8, line 56, col 9, line 26] is greater than or equal to 4.9 eV.
Zang teaches an integrated circuit (107) fig. 5 [0056] wherein a work function of the P-type gate all around transistor (107) [0056] is greater than or equal to 4.9 eV (preferably work function energy satisfies: 4.9 eV < work function energy < 5.2 eV – greater than 4.9 eV for p-type gate all around [0056]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit of Ando such that the p-type gate all around transistor explicitly has a work function greater than 4.9 eV and less than 5.2 eV [0056] in order to optimize the work function of gate all around transistor [0056] according to art recognized parameters [0056], as taught by Zang. 10. Claims 5-7 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ando (U.S. Patent No 10,332,809) modified by Wang (U.S. PG Pub No US2019/0237336A1), as applied in claims 4 and 14 above, and further in view of Xie (U.S. PG Pub No US2020/0274000A1).
Regarding claim 5, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 4. However, Ando does not explicitly disclose wherein the metal gate layer (comprising 20L and 20R) fig. 5 [col 7, lines 34-55] (comprising titanium metal) includes carbon and one or more of titanium and tantalum.
Xie teaches an integrated circuit (200) fig. 15A [0144] wherein the metal gate layer (1402) fig. 15A [0141] includes carbon and one or more of titanium and tantalum (may include combination of titanium and tantalum carbide instead of titanium nitride [0141]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit of Ando such that the metal gate material comprises additional elemental additives such as carbon, silicon, tantalum, etc. [0141] in order to favorably vary the conductivity properties of the gate [0141, 0143] resulting from the particular combination of conductive additives [0141], as taught by Xie.
Regarding claim 6, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 5. However, Ando does not explicitly disclose wherein the metal gate fill material (26) fig. 5 [col 8, lines 53-67] includes nitrogen and titanium (nickel silicide instead [col 8, lines 55-67]).
Xie teaches an integrated circuit (200) fig. 15A [0144] wherein the metal gate fill material (1402) fig. 15A [0141] includes nitrogen and titanium (may include combination of nickel silicide and titanium nitride [0141]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit of Ando such that the metal gate material comprises additional elemental additives such as carbon, silicon, tantalum, etc. [0141] in order to favorably vary the conductivity properties of the gate [0141, 0143] resulting from the particular combination of conductive additives [0141], as taught by Xie.
Regarding claim 7, Ando in view of Wang and Xie teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 6. Ando in view of Wang (with reference to Wang) also teaches wherein the passivation layer (20) fig. 11 [0031-0032] includes a different material than the metal gate layer (25) fig. 11 [0030] (could be formed of distinct nitride materials with different etch selectivity [0030] – i.e, 20 could be TiN and 25 could be TaN [0030], comprising different metal elements).
Regarding claim 16, Ando in view of Wang teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 14. However, Ando does not explicitly disclose wherein the first metal gate layer (20R) fig. 5 [col 7, lines 34-41] includes carbon and titanium (titanium nitride TiN [col 7, lines 35-54]).
Xie teaches an integrated circuit (200) fig. 15A [0144] wherein the metal gate layer (1402) fig. 15A [0141] includes carbon and one or more of titanium and tantalum (may include combination of titanium and tantalum carbide instead of titanium nitride [0141]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit of Ando such that the metal gate material comprises additional elemental additives such as carbon, silicon, tantalum, etc. [0141] in order to favorably vary the conductivity properties of the gate [0141, 0143] resulting from the particular combination of conductive additives [0141], as taught by Xie.
Regarding claim 17, Ando in view of Wang and Xie teaches the integrated circuit [see fig. 5, col 8, lines 53-67] of claim 16. Ando also teaches wherein the second metal gate layer (20L) fig. 5 [col 7, lines 34-41] includes nitrogen and titanium (titanium nitride TiN [col 7, lines 35-45]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature GAA-FETs with gate dielectric layers surrounded by metal gate layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEAN AYERS WINTERS/Examiner, Art Unit 2892 08/05/2026
Prosecution Insights