DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 8 is objected to because of the following informalities: claim 8 recites “electrically coupled to the second conductive feature.” However, there is no first instance of “a second conductive feature” in claim 1, i.e. there is a lack of antecedent basis for “the second conductive feature”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 6, 8, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Won et al. 9US 20080050874 A1, hereinafter Won)
With regards to claim 1, Won discloses a method for fabricating a semiconductor device (FIGS. 1a-6i) comprising:
forming a first conductive feature (wiring line 121) on a semiconductor substrate; (substrate 111)
forming a first via structure (via comprising narrow portion of wiring layer 123) over the first conductive feature;
forming a first metallization structure (wider portion of wiring layer 123) over the first via structure, wherein the first metallization structure is conductively coupled to the first conductive feature through the first via structure;
forming a conductive etch stop structure (metal capping layer 170/180) on the first metallization structure;
forming a first via hole (hole comprising bottom portion 124) above the conductive etch stop structure and a second via hole (via hole comprising capacitor 132/140/150) adjacent the first via hole, wherein the first via hole exposes the conductive etch stop structure; and
forming a capacitor (capacitor 130/140/150) in the second via hole. (See FIG. 1a)
With regards to claim 2, Won discloses the method according to claim 1 further comprising:
forming a second conductive feature (wiring 131) on the semiconductor substrate, wherein the second via hole is located above the second conductive feature;
forming a second via structure (bottom structure 124) within the first via hole; and
forming a second metallization structure (structure 125) above the second via structure.
With regards to claim 4, Won discloses the method according to claim 1, wherein the conductive etch stop structure comprises titanium nitride (TiN). (Paragraph [0044]: “The barrier layers 170 can be at least one of Ti, TiN…”)
With regards to claim 6, Won discloses the method according to claim 1, wherein the first electrode of the capacitor is formed along the sidewalls and bottom surface of the second via hole. (See FIG. 1a)
With regards to claim 8, Won discloses the method according to claim 1, wherein the first electrode (electrode 132) of the capacitor is electrically coupled to [[the]] a second conductive feature (conductive feature 131) on the semiconductor substrate.
With regards to claim 15, Won discloses a method of making a semiconductor device, (FIGS. 1a-6i) comprising:
forming a plurality of metallization structures (structures comprising layers of 122) electrically coupled through a plurality of via structures (vias comprising layers 122) in a plurality of dielectric layers; (dielectrics 112-115)
forming a plurality of conductive etch stop structures (stop structures 180) on the plurality of metallization structures; and
forming a plurality of capacitors (capacitors 130-150) embedded and oriented transversely in the plurality of dielectric layers,
wherein each of the capacitors comprises a capacitor dielectric layer dielectrics 150) sandwiched between first and second metal electrodes. (See FIG. 1a)
Allowable Subject Matter
Claims 9-14 are allowed.
Claims 3, 5, 7, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. (US 20150102461 A1) – vias in a DRAM structure
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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