DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/25/2024 and 05/14/2026 was filed after the mailing date of the application on 07/25/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al, US 20150348874 A1 ( Tsai ‘874).
Regarding claim 1; Tsai ‘874 teaches a method, comprising:
forming, over a substrate ( Tsai ‘874: Annotated Fig (3H) shared in this OA: Substrate), an interconnect structure (508a-508f + 538a-538f, 514, 512, 502, 504, 506, 606) comprising:
a plurality of intermetal dielectric (IMD) layers (504, [0059]: “… the first IMD layers 504”);
a plurality of etch stop layers interleaving the plurality of IMD layers (Annotated Fig (1B) shared in this OA: 104, [0022]: “It should also be noted that one or more etch stop layers (not shown) may be positioned between adjacent layers of the first workpiece 100, e.g., the first IMD layers 104 and the first substrate 102, or between individual layers of the first IMD layers 104.”, it is worth noting that structure 104 is relabeled in later figures as 504);
a guard ring structure (508a-508f + 538a-538f, [0063]: “In some embodiments, the first conductive lines 508 and first conductive vias 538 collectively form a seal ring structure surrounding the conductive plug 528.”) extending through the plurality of IMD layers (504, [0059]: “… the first IMD layers 504”) and the plurality of etch stop layers (Annotated Fig (1B) shared in this OA: 104, [0022]: “It should also be noted that one or more etch stop layers (not shown) may be positioned between adjacent layers of the first workpiece 100, e.g., the first IMD layers 104 and the first substrate 102, or between individual layers of the first IMD layers 104.”, it is worth noting that structure 104 is relabeled in later figures as 504), the guard ring structure (508a-508f + 538a-538f) having a cylindrical shape and defining a metal-free center region (Annotated Fig (1B) shared in this OA: region in which the opening 110 is formed);
forming a first opening (110) through the metal-free center region (region in which the first opening 110 is formed); extending the first opening (110) into the substrate (Substrate) to form a second opening (Fig (1C): 118);
forming a via structure (Fig (3H): via structure occupied by 528) in the second opening (Fig (1C): 118 which becomes the via opening occupied by 528 later in the process);
depositing a top dielectric layer (Fig (3H): 502) over the via structure (528) and the guard ring structure (508a-508f + 538a-538f); and
forming a top metal feature (Metal Feature = top portion of 528) in the top dielectric layer (502) directly over top surfaces of the via structure (Via Structure = bottom portion of 528) and the guard ring structure (508a-508f + 538a-538f).
PNG
media_image1.png
880
986
media_image1.png
Greyscale
PNG
media_image2.png
789
887
media_image2.png
Greyscale
Regarding claim 2; Tsai ‘874 teaches all the limitations of the method of claim 1.
Further, Tsai ‘874 teaches wherein the interconnect structure ( Tsai ‘874: Annotated Fig (3H): 508a-508f + 538a-538f, 514, 512, 502, 504, 506, 606) comprises a number of metallization layers (508a-508f + 538a-538f) disposed in the plurality of IMD layers (504, [0059]: “… the first IMD layers 504”) and the plurality of etch stop layers (Annotated Fig (1B) shared in this OA: 104, [0022]: “It should also be noted that one or more etch stop layers (not shown) may be positioned between adjacent layers of the first workpiece 100, e.g., the first IMD layers 104 and the first substrate 102, or between individual layers of the first IMD layers 104.” , it is worth noting that structure 104 is relabeled in later figures as 504), wherein the number is between eight (8) and thirteen (13) (counting the features 508a-508f + 538a-538f we find their number to be 12 which is within the recited range).
Regarding claim 3; Tsai ‘874 teaches all the limitations of the method of claim 2.
Further, Tsai ‘874 teaches wherein the guard ring structure ( Tsai ‘874: Annotated Fig (3H) shared in this OA: 508a-508f + 538a-538f) comprises the number of ring layers stacked vertically one over another.
Regarding claim 4; Tsai ‘874 teaches all the limitations of the method of claim 3.
Further, Tsai ‘874 teaches wherein each of the number of ring layers ( Tsai ‘874: Annotated Fig (3H) shared in this OA: 508a-508f + 538a-538f) includes a lower portion (508a-508f) and an upper portion (538a-538f) on the lower portion (508a-508f), wherein a dimension of the lower portion (508a-508f) is different from a dimension of the upper portion (538a-538f).
Regarding claim 5; Tsai ‘874 teaches all the limitations of the method of claim 1.
Further, Tsai ‘874 teaches wherein the guard ring structure ( Tsai ‘874: Annotated Fig (3H) shared in this OA: 508a-508f + 538a-538f) is not exposed in the first opening (opening occupied by the structure 528).
Regarding claim 6; Tsai ‘874 teaches all the limitations of the method of claim 1.
Tsai ‘874 teaches further comprising: before the forming of the first opening ( Tsai ‘874: Fig (1B): 110), depositing a top ESL (109, [0028]: “… In the illustrated embodiment, the first STI region 109 is used as an etch stop layer,…”) over the interconnect structure (108a-108f); depositing a top IMD layer (102) over the top ESL (109); and forming a coupling structure (112+114) in the top ESL (109) and the top IMD layer (102), wherein the coupling structure (112+114) is disposed directly over the guard ring structure (108a-108f)
Regarding claim 7; Tsai ‘874 teaches all the limitations of the method of claim 6.
Tsai ‘874 teaches wherein the first opening ( Tsai ‘874: Fig (1B): 110) extends through the top IMD (102) layer and the top ESL (109).
Regarding claim 11; Tsai ‘874 teaches all the limitations of the method of claim 1.
Tsai ‘874 teaches further comprising: after the extending of the first opening ( Tsai ‘874: Fig (1B): 110), performing an etch process to smooth sidewalls of the second opening (Fig (1C): 118, [0034]: “an anisotropic wet etch, or any other suitable anisotropic etch or patterning process, may be performed on the semiconductor device to form a second opening 118.”).
Regarding claim 12; Tsai ‘874 teaches a method, comprising:
forming, over a substrate ( Tsai ‘874: Annotated Fig (3H) shared in this OA: 502),
an interconnect structure (508a-508f + 538a-538f, 514, 512, 502, 504, 506, 606) comprising: a plurality of intermetal dielectric (IMD) layers (504, [0059]: “… the first IMD layers 504”);
a plurality of etch stop layers interleaving the plurality of IMD layers (Annotated Fig (1B) shared in this OA: 104, [0022]: “It should also be noted that one or more etch stop layers (not shown) may be positioned between adjacent layers of the first workpiece 100, e.g., the first IMD layers 104 and the first substrate 102, or between individual layers of the first IMD layers 104.”, it is worth noting that structure 104 is relabeled in later figures as 504);
a guard ring structure (508a-508f + 538a-538f) extending through the plurality of IMD layers (504, [0059]: “… the first IMD layers 504”) and the plurality of etch stop layers (Annotated Fig (1B) shared in this OA: 104, [0022]: “It should also be noted that one or more etch stop layers (not shown) may be positioned between adjacent layers of the first workpiece 100, e.g., the first IMD layers 104 and the first substrate 102, or between individual layers of the first IMD layers 104.”, it is worth noting that structure 104 is relabeled in later figures as 504),
the guard ring structure (508a-508f + 538a-538f) having a cylindrical shape and defining a metal-free center region (center region between 508a-508f and 538a-538f later occupied by 529);
depositing a top ESL (509) over the interconnect structure(508a-508f + 538a-538f, 514, 512, 502, 504, 506, 606);
depositing a top IMD layer (502) over the top ESL (509);
forming a coupling structure (512+514) in the top ESL (509) and the top IMD layer (502),
forming a first opening (Annotated Fig (1B) shared in this OA: 110) through the metal-free center region (Region between 108a – 108f) and a center region of the coupling structure (112+114);
extending the first opening (110) into the substrate (Annotated Fig (3H) shared in this OA: Substrate) to form a second opening (118);
smoothing sidewalls of the second opening (Fig (1C): 118) to form a third opening (bottom part of 118);
forming a via structure (Fig (3H): 529) in the third opening (Fig (1C): bottom part of 118);
depositing a top dielectric layer (502) over the via structure (Via Structure = bottom portion of 528) and the guard ring structure (508a-508f + 538a-538f); and
forming a top metal feature (Metal Feature = top part of 528) in the top dielectric layer (502) to interface top surfaces of the via structure (Via Structure = bottom portion of 528) and the coupling structure (512+514).
Regarding claim 13; Tsai ‘874 teaches all the limitations of the method of claim 12.
Further, Tsai ‘874 teaches wherein the interconnect structure ( Tsai ‘874: Annotated Fig (3H): 508a-508f + 538a-538f, 514, 512, 502, 504, 506, 606) comprises a number of metallization layers (508a-508f + 538a-538f) disposed in the plurality of IMD layers (504, [0059]: “… the first IMD layers 504”) and the plurality of etch stop layers (Annotated Fig (1B) shared in this OA: 104, [0022]: “It should also be noted that one or more etch stop layers (not shown) may be positioned between adjacent layers of the first workpiece 100, e.g., the first IMD layers 104 and the first substrate 102, or between individual layers of the first IMD layers 104.”, it is worth noting that structure 104 is relabeled in later figures as 504), wherein the number is between eight (8) and thirteen (13) (counting the features 508a-508f + 538a-538f we find their number to be 12 which is within the recited range).
Regarding claim 14; Tsai ‘874 teaches all the limitations of the method of claim 13.
Further, Tsai ‘874 teaches wherein the guard ring structure ( Tsai ‘874: Annotated Fig (3H) shared in this OA: 508a-508f + 538a-538f) comprises the number of ring layers stacked vertically one over another.
Regarding claim 15; Tsai ‘874 teaches all the limitations of the method of claim 14.
Further, Tsai ‘874 teaches wherein each of the number of ring layers ( Tsai ‘874: Annotated Fig (3H) shared in this OA: 508a-508f + 538a-538f) includes a lower portion (508a-508f) and an upper portion (538a-538f) on the lower portion (508a-508f), wherein a dimension of the lower portion (508a-508f) is different from a dimension of the upper portion (538a-538f).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al, US 20150348874 A1 ( Tsai ‘874) in view of Schlaffer et al, US 20210337653 A1 (Schlaffer).
Regarding claim 8; Tsai ‘874 teaches all the limitations of the method of claim 6.
However, Tsai ‘874 does not teach wherein the coupling structure comprises titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), or aluminum (Al).
Schlaffer teaches wherein the coupling structure (Sclaffer: Fig (9): 140) comprises copper (Cu) ([0021]: “In another example, the thermally conductive coupling medium comprises an electrically conductive coupling structure such as a copper layer and/or one or more (copper filled) (micro) vias. In this manner, the thermally conductive coupling medium can be also an efficient electrically conductive material.”).
Tsai ‘874 and Schlaffer are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Tsai ‘874 by making the coupling structure out of copper as disclosed in Schlaffer to improve the thermal conductivity of the connection structures leading to more heat dissipation from within the device which leads to an increased longevity of the device.
Regarding claim 16; Tsai ‘874 teaches all the limitations of the method of claim 12.
However, Tsai ‘874 does not teach wherein the top metal feature comprises copper, cobalt, nickel, aluminum, or an aluminum-copper alloy.
Schlaffer teaches wherein the coupling structure (Sclaffer: Fig (9): 140) comprises copper (Cu) ([0021]: “In another example, the thermally conductive coupling medium comprises an electrically conductive coupling structure such as a copper layer and/or one or more (copper filled) (micro) vias. In this manner, the thermally conductive coupling medium can be also an efficient electrically conductive material.”).
Tsai ‘874 and Schlaffer are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Tsai ‘874 by making the coupling structure out of copper as disclosed in Schlaffer to improve the thermal conductivity of the connection structures leading to more heat dissipation from within the device which leads to an increased longevity of the device.
PNG
media_image3.png
751
575
media_image3.png
Greyscale
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al, US 20150348874 A1 ( Tsai ‘874) in view Tokashiki et al, US 20210143055 A1 (Tokashiki).
Regarding claim 9; Tsai ‘874 teaches all the limitations of the method of claim 1.
However, Tsai ‘874 does not teach wherein the forming of the first opening comprises use of an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, an iodine-containing gas, or a combination thereof.
Tokashiki teaches wherein the forming of the first opening (Tokashiki: Fig (2): 105) comprises use of an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, an iodine-containing gas, or a combination thereof (Claim 17: “A method of forming high aspect ratio openings, comprising: substantially simultaneously introducing an etch gas…, the etch gas comprising: at least one material selected from the group consisting of:… chlorine (Cl.sub.2), hydrogen bromide (HBr), hydrogen tetrabromide, bromine trifluoride (BrF.sub.3), bromine octofluoride (BrF.sub.8), bromine heptafluoride (BrF.sub.7).”).
Tsai ‘874 and Tokashiki are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Tsai ‘874 by using the gases disclosed in Tokashiki to etch the first opening to ensure the selective etching process keeps the rest of the structure intact leading to a more reliable device.
Regarding claim 10; Tsai ‘874 in view of Tokashiki teaches all the limitations of the method of claim 9.
Tsai ‘874 does not teach wherein the extending of the first opening comprises use of a cyclic etch process that includes a plurality of etch cycles and a plurality of deposition cycles.
Tokashiki teaches wherein the extending of the first opening (Tokashiki: Fig (2): 105) comprises use of a cyclic etch process that includes a plurality of etch cycles and a plurality of deposition cycles ([0028]: “… The HAR openings 105 and protective material 115 may also be formed in a cyclic fashion…”).
Tsai ‘874 and Tokashiki are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person of ordinary skill in the art, to modify Tsai ‘874 by using a cyclic process to extend the first opening as disclosed in Tokashiki to establish better control over the dimensions of the opening and its extensions as disclosed leading to a more reliable device production process.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al, US 20150348874 A1 ( Tsai ‘874) in view of Liu, US 11094650 B1 (Liu) in further view of Tsai, US 20210036097 A1 (Tsai ‘097).
Regarding claim 17; Tsai ’874 teaches a method, comprising:
forming over a substrate (Tsai ‘874: Annotated Fig (3H) shared in this OA: Substrate) an interconnect structure (508a-508f + 538a-538f, 514, 512, 502, 504, 506, 606) comprising:
a plurality of etch stop layers (Annotated Fig (1B) shared in this OA: 104, [0022] It should also be noted that one or more etch stop layers (not shown) may be positioned between adjacent layers of the first workpiece 100, e.g., the first IMD layers 104 and the first substrate 102, or between individual layers of the first IMD layers 104.”),
a plurality of intermetal dielectric (IMD) layers (504, [0059]: “… the first IMD layers 504”) interleaving the plurality of etch stop layers (Annotated Fig (1B) shared in this OA: 104, [0022]: “It should also be noted that one or more etch stop layers (not shown) may be positioned between adjacent layers of the first workpiece 100, e.g., the first IMD layers 104 and the first substrate 102, or between individual layers of the first IMD layers 104.”), and
a plurality of guard ring layers (508a-508f + 538a-538f) stacked one over another to form a guard ring structure (508a-508f + 538a-538f),
each of the plurality of guard ring layers (508a-508f + 538a-538f) being disposed within one of the plurality of etch stop layers and one of the plurality of IMD layers immediately overlying the one of the plurality of etch stop layers;
etching an opening (Annotated Fig (1B) shared in this OA: 110) through the plurality of etch stop layers, the plurality of IMD layers (Annotated Fig (3H) shared in this OA: 504, [0059]: “… the first IMD layers 504”) and a portion of the substrate (Substrate);
forming a via structure (Via Structure = lower portion of 528) within the opening Annotated Fig (1B) shared in this OA: 110);
depositing a dielectric layer (502) over the via structure (Via Structure = lower portion of 528) and the guard ring structure (508a-508f + 538a-538f); and
forming a top metal feature (Metal Feature = top portion of 528) in the dielectric layer (502) such that the top metal feature (Metal Feature = top portion of 528) spans over and directly contacts the via structure (Via Structure = lower portion of 528) and the guard ring structure.
Tsai ‘874 does not teach each of the plurality of guard ring layers being disposed within one of the plurality of etch stop layers and one of the plurality of IMD layers immediately overlying the one of the plurality of etch stop layers.
Liu teaches each of the plurality of guard ring layers (Liu: Fig (11): 118) being disposed within one of the plurality of etch stop layers (136) and one of the plurality of IMD layers (114, 120, 122) immediately overlying the one of the plurality of etch stop layers (136).
Tsai ‘874 and Liu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Tsai ‘874 by constructing the guard ring layers in between the IMD layers and the etch stop layers as disclosed in Liu to improve the control of etching the various structures through utilizing the anisotropic etching characteristics associated with using etch stop layers to ensure achieving the desired shapes and sizes for the structures leading to a more reliable device.
PNG
media_image4.png
832
609
media_image4.png
Greyscale
And while Tsai ‘874 teaches that the top metal feature (Tsai ‘874: Annotated Fig (3H): Metal Feature = top portion of 528) spans over and directly contacts the via structure (Via Structure = lower portion of 528) , Tsai ‘874 in view of Liu fails to teach that the top metal feature spans over and directly contacts the guard ring structure.
Tsai ‘097 teaches that the top metal feature (Tsai ‘097: Fig (9): 905A) spans over and directly contacts the guard ring structure (907).
Tsai ‘874 in view of Liu and Tsai ‘097 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Tsai’ 874 in view of Liu by making the metal feature span over and contact the ring structure as disclosed in Tsai 097 to establish electrical connections between some of ground points and the guard rings to enhance the effect of electrical shielding that the guard rings can play leading to a more reliable device.
Regarding claim 18; Tsai ‘874 in view of Liu in further view of Tsai ‘097 teaches all the limitations of the method of claim 17.
Further, Tsai ‘874 teaches wherein the opening (Tsai: Annotated Fig (1B) shared in this OA: 110) and the guard ring structure (108a – 108f) are circular (Annotated Fig (1E) shared in this OA) when viewed along a direction perpendicular to the substrate (Annotated Fig (1B) shared in this OA: Substrate), wherein the opening (110) comprises a first diameter (W4, [0047]: “… W.sub.4 may be between about 1.0 μm and about 8.0 μm”) and the guard ring structure (108a – 108f) comprises a second diameter (W5, [0047]: “W.sub.5 may be between about 1.2 μm and about 11 μm”), wherein the second diameter (W5, [0047]: “…W.sub.5 may be between about 1.2 μm and about 11 μm”) is greater than the first diameter (W4, [0047]: “W.sub.4 may be between about 1.0 μm and about 8.0 μm”) by between 0.4 µm and about 1.0 µm.
PNG
media_image5.png
881
838
media_image5.png
Greyscale
Regarding claim 19; Tsai ‘874 in view of Liu in further view of Tsai ‘097 teaches all the limitations of the method of claim 17.
Further, Tsai ‘874 teaches wherein, along a radial direction of the via structure (Tsai: Fig (1D): bottom portion of 128), the via structure (bottom part of 128) is spaced apart from the guard ring structure (108a – 108f) a spacing between about 0.2 µm and about 0.5 µm (by examining Fig (1D) in combination with paragraph [0047] we notice that the via structure can be identified with a radial distance corresponding to W3 where W3 may be between may be between about 0.8 μm and about 6.0 μm and that guard ring structure can be associated with the dimension W5 where W5 may be between about 1.2 μm and about 11 μm. The difference between these two dimensions falls within the specified range in the limitations recited in the claim.”).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al, US 20150348874 A1 ( Tsai ‘874) in view of Liu, US 11094650 B1 (Liu) in further view of Tsai, US 20210036097 A1 (Tsai ‘097) in further view of Lin, P., Xie, X., Wang, Y. et al. A multi-step etch method for fabricating slightly tapered through-silicon vias based on modified Bosch process. Microsyst Technol 25, 2693–2698 (2019). https://doi.org/10.1007/s00542-018-4249-8.
Regarding claim 20; Tsai ‘874 in view of Liu in further view of Tsai ‘097 teaches all the limitations of the method of claim 17.
Further, Tsai ‘874 wherein the etching comprises: etching through the plurality of etch stop layers (Tsai ‘874: Annotated Fig (1B): 109) and the plurality of IMD layers (102) using a first etch process ([0017]: “… In the illustrated embodiment, the first substrate 102 is patterned using, for example, photolithographic masking and etching process to form openings in the first substrate 102…”) to form a pilot opening (110); extending the pilot opening into the substrate (Substrate) using a second etch process different from the first etch process; and smoothing surfaces of the extended pilot opening (110) using a third etch process to form the opening ([0034] FIG. 1C illustrates the semiconductor device shown in FIG. 1B after one or more additional etching processes are performed in accordance with an embodiment. A suitable etching process, such as a dry etch, an anisotropic wet etch, or any other suitable anisotropic etch or patterning process, may be performed on the semiconductor device to form a second opening 118”).
Tsai ‘874 in view of Liu in further view of Tsai ‘097 does not teach using a second etch process different from the first etch process.
However, Lin teaches using a second etch process different from the first etch process Lin: See the experimental section of the paper: “In this case, the processing of tapered via formation is performed using a modified Bosch cycle that consists of five separate steps: (1) octafluorocyclobutane (C4F8) deposition, (2) anisotropic sulfur hexafluoride (SF6) etching to remove the bottom passivation, (3) short anisotropic SF6 etching, (4) isotropic SF6 etching with descending time to achieve the tapered sidewalls, (5) short anisotropic SF6 etching again.”).
Tsai ‘874 in view of Liu in further view of Tsai ‘097 and Lin are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person of ordinary skill in the art, to modify Tsai ‘874 in view of Liu in further view of Tsai ‘097 by using different etching methods to expand the pilot opening as disclosed in Lin to improve the control over the size of the sidewalls of the vias to prevent current leakage and improve the reliability and longevity of the device.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Lu et al, US 8890293 B2 (Lu); teaches a guard ring that has a via in its center where the guard ring components are in different IMD layers. Also, Lu teaches the guard ring appears to be circular when seen along a direction that perpendicular to the top surface of the substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.K./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
Prosecution Insights