DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) submitted on July 25, 2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “the logic component, the passive component, and the through oxide via at least partially overlap with each other from a plan view,” as recited in claim 16, must be shown or the feature(s) canceled from the claim(s). Figs. 1, 27-30, 37-40 and 43-45 are cross-sectional views. Applicant’s drawings do not include a plan view (i.e., a top view) of the logic component, the passive component and the through oxide via. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 5, 8-10 and 17 are objected to because of the following informalities:
“is stacked” should read “are stacked” (claim 5, line 2);
“the via” should read “the first via” (claim 8, line 1);
“is stacked” should read “are stacked” (claim 9, line 2);
“MIN” should read “MIM” (claim 10, line 12);
the period after “the front side” must be changed to a comma (claim 10, line 12);
“Wherein” should read “wherein” (lowercase) (claim 10, line 13);
“The method” should read “A method” (claim 17, line 1);
“the gate-all-around transistor” should read “the GAA FET” (claim 17, line 14).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0058628 A1 (hereinafter “Slovin”) in view of US 2022/0139911 A1 (hereinafter “Wei”).
Regarding claim 1, Slovin discloses a method, comprising:
forming a transistor (34; Fig. 2; [0025]) on a first substrate (22; Fig. 2; [0023]);
forming a first metal layer (42; Fig. 2; [0023]) on the transistor;
forming a first oxide layer (32; Fig. 2; [0026]) on the first metal layer; and
bonding the first oxide layer to a second oxide layer (66; Fig. 4; [0032]) on a second substrate (60; Fig. 4; [0027]).
Slovin does not disclose the transistor is a gate-all-around field effect transistor (GAA FET), and exposing a portion of the GAA FET by removing one or more layers of the first substrate.
Wei teaches the transistor (377; Fig. 3K; [0077] and [0096]-[0097]) is a gate-all-around field effect transistor (GAA FET), and
exposing a portion (366; Fig. 3O; [0106]) of the GAA FET by removing one or more layers of the first substrate (350, 352; Figs. 3M-3N; [0100]-[0105]).
Slovin and Wei are analogous art because they both are directed to semiconductor devices and methods of manufacturing the same and one of ordinary skill in the art would have had a reasonable expectation of success to modify Slovin with the specified features of Wei because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a gate-all-around field effect transistor (GAA FET), and to expose a portion of the GAA FET by removing one or more layers of the first substrate, as taught by Wei, in order to realize one or more advantages of a GAA FET such as improved electrostatic control of the channel by the gate, reduced leakage current and higher drive current, and in order to form a backside contact for backside power delivery, which is key to further standard cell scaling (Wei: [0016]).
Claim(s) 10, 11, 13, 14 and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0296396 A1 (hereinafter “Wu”) in view of US 2020/0365195 A1 (hereinafter “Couet”) and US 2019/0267463 A1 (hereinafter “Chao”).
Regarding claim 10, Wu discloses in Fig. 3 and related text a method, comprising:
forming a logic component (30, 40; [0032]; note: reference numeral 30 has been omitted from Fig. 3) on a substrate (2; [0033]), the logic component including a gate-all-around transistor (30; [0032]) and a thin film transistor (40; [0032]);
forming a passive component (20; [0021] and [0036]) on the substrate; and
forming a through oxide via (10; [0019]) to electrically connect the logic component to the passive component,
wherein the passive component has a front side (a top side) and a back side (a bottom side) opposite the front side.
Wu does not explicitly disclose the passive component including a metal-insulator-metal (MIM) structure, wherein the gate-all-around transistor includes a gate electrode, a source region, and a drain region, wherein either the source region or the drain region of the gate-all-around transistor includes a first side and a second side opposite the first side.
Moreover, Wu does not disclose, in the embodiment of Fig. 3, the logic component is disposed between the substrate and the passive component.
Couet teaches in Fig. 1b and related text the passive component (108; [0039]) including a metal-insulator-metal (MIM) structure (130, 140, 150; [0052]-[0054]).
Chao teaches in Fig. 9 and related text the gate-all-around transistor includes a gate electrode (904; [0039]), a source region (702 (one of the two); [0035]), and a drain region (702 (the other of the two); [0035]), and either the source region or the drain region of the gate-all-around transistor includes a first side (e.g., a bottom side) and a second side (e.g., a top side) opposite the first side.
Wu teaches, in the embodiment of Fig. 4, the logic component (30 (covered by interlayer dielectric (ILD) 11 but not shown in Fig. 4), 430; [0013], [0032], [0039] and [0040]) is disposed between the substrate (2 (under ILD 11 and GAA FET 30 but not shown in Fig. 4); [0033]) and the passive component (420; [0039]).
Wu, Couet and Chao are analogous art because they each are directed to semiconductor devices and methods of manufacturing the same and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu with the specified features of Couet and Chao because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the passive component to include a metal-insulator-metal (MIM) structure, as taught by Couet, to form the gate-all-around transistor to include a gate electrode, a source region, and a drain region, wherein either the source region or the drain region of the gate-all-around transistor includes a first side and a second side opposite the first side, as taught by Chao, and to arrange the logic component between the substrate and the passive component, as taught by Wu in the embodiment of Fig. 4, (1) because a conventional magnetic random access memory (MRAM) includes a magnetic tunnel junction (MTJ) including a reference layer (ferromagnetic metal) and a free layer (ferromagnetic metal) spaced apart by a tunnel barrier layer (dielectric oxide), (2) in order to provide the gate-all-around transistor as a field-effect gate all around transistor having three terminals (gate, source and drain), and (3) in order to shorten the vertical distance between the gate-all-around transistor and the thin film transistor, thereby reducing a resistance-capacitance (RC) delay for electrical signals propagating therebetween.
Regarding claim 11, Wu in view of Couet and Chao disclose the back side of the MIM structure faces the gate-all-around transistor and the thin film transistor (Wu: Fig. 4; note: the gate-all-around transistor is under ILD 11 but not illustrated in Fig. 4).
Regarding claim 13, Wu in view of Couet and Chao disclose the through oxide via includes copper (Wu: [0019]).
Regarding claim 14, Wu in view of Couet and Chao disclose the through oxide via includes a first end (a top end) and a second end (a bottom end) opposite the first end, the first end of the through oxide via is connected to the MIM structure and the second end of the through oxide via extends past the MIM structure and connects to the logic component (Wu: Figs. 3, 4; [0036] and [0038]).
Regarding claim 16, Wu in view of Couet and Chao disclose the logic component, the passive component, and the through oxide via at least partially overlap with each other from a plan view (although Fig. 3 of Wu is a cross-sectional view rather than a plan view, it nevertheless shows that the logic component, the passive component, and the through oxide via at least partially overlap with each other in a vertical direction which is a stacking direction of these elements).
Regarding claim 17, Wu discloses in Fig. 3 and related text a method, comprising:
forming a gate-all-around field effect transistor (GAA FET) (30; [0032]) on a substrate (2; [0033]), the GAA FET including:
a first metal layer (8; [0033]); and
a second metal layer (12B; [0035]) on the first metal layer;
vertically stacking a thin film transistor (TFT) (40; [0032]) on the GAA FET;
forming a passive component (20; [0036]) on the GAA FET;
forming a through oxide via (10; [0019]) having a first end (a top end) and a second end (a bottom end),
wherein the first end of the through oxide via is electrically connected to the passive component ([0036]), and
wherein the second end of the through oxide via is electrically connected to at least one of the first metal layer or the second metal layer of the GAA FET ([0035]).
Wu does not explicitly disclose the passive component includes a metal-insulator-metal (MIM) structure, and the gate-all-around transistor includes a multi-layer stack including a plurality of semiconductor layers.
Moreover, Wu does not disclose, in the embodiment of Fig. 3, the thin film transistor is disposed between the passive component and the GAA FET.
Couet teaches in Fig. 1b and related text the passive component (108; [0039]) includes a metal-insulator-metal (MIM) structure (130, 140, 150; [0052]-[0054]).
Chao teaches in Fig. 9 and related text the gate-all-around transistor includes a multi-layer stack including a plurality of semiconductor layers (104; [0001] and [0023]).
Wu teaches, in the embodiment of Fig. 4, the thin film transistor (430; [0039]) is disposed between the passive component (420; [0039]) and the GAA FET (30 (under ILD 11 but not illustrated in Fig. 4); [0032]).
Wu, Couet and Chao are analogous art because they each are directed to semiconductor devices and methods of manufacturing the same and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu with the specified features of Couet and Chao because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the passive component to include a metal-insulator-metal (MIM) structure, as taught by Couet, to form the gate-all-around transistor to include a multi-layer stack including a plurality of semiconductor layers, as taught by Chao, and to form the thin film transistor between the passive component and the GAA FET, as taught by Wu in the embodiment of Fig. 4, (1) because a conventional magnetic random access memory (MRAM) includes a magnetic tunnel junction (MTJ) including a reference layer (ferromagnetic metal) and a free layer (ferromagnetic metal) spaced apart by a tunnel barrier layer (dielectric oxide), (2) in order to realize one or more advantages of a gate-all-around transistor such as improved electrostatic control of the channel by the gate, reduced leakage current and higher drive current, and (3) in order to shorten the vertical distance between the gate-all-around transistor and the thin film transistor, thereby reducing a resistance-capacitance (RC) delay for electrical signals propagating therebetween.
Regarding claim 18, Wu in view of Couet and Chao disclose the substrate, the GAA FET, the thin film transistor, and the MIM structure are stacked so that the GAA FET, the thin film transistor, and the MIM structure at least partially overlap each other (Wu: Fig. 3).
Regarding claim 19, Wu in view of Couet and Chao disclose the GAA FET and the TFT are vertically adjacent to each other without any MIM structure therebetween (Wu: Fig. 4; note: although the GAA FET is under ILD 11 as shown in Fig. 3, the GAA FET is not illustrated in Fig. 4).
Allowable Subject Matter
Claims 2-9, 12, 15 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, individually or in combination, does not teach or suggest at least the limitations “forming a thin film transistor overlying the contact plug” as recited in claim 2, “forming a thin film transistor overlying the second via” as recited in claim 6, “the through oxide via extends from the front side of the MIM structure and contacts the second side of either the source region or the drain region of the gate-all-around transistor” as recited in claim 12, “an extended portion of the through oxide via between the first end and the second end of the through oxide via is laterally spaced apart from the MIM structure” as recited in claim 15, and “the through oxide via includes an extended portion between the first end and the second end, the extended portion of the through oxide via is laterally spaced apart from the GAA FET, the thin film transistor, and the MIM structure” as recited in claim 20. Claims 3-5 depend from claim 2 and therefore would be allowable at least by virtue of their dependency. Claims 7-9 depend from claim 6 and therefore would be allowable at least by virtue of their dependency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811
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