Prosecution Insights
Last updated: April 19, 2026
Application No. 18/784,854

MEMORY POWER CONTROL BY ENABLE CIRCUIT

Non-Final OA §DP
Filed
Jul 25, 2024
Examiner
BEGUM, SULTANA
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
To Grant
94%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allow Rate
486 granted / 522 resolved
+25.1% vs TC avg
Minimal +0% lift
Without
With
+0.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
32 currently pending
Career history
554
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
16.9%
-23.1% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 522 resolved cases

Office Action

§DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of claim(s) to be treated in this office action: a. Independent: 1, 11 and 18 b. Pending: 1-20 Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Information Disclosure Statement The information disclosure statement (IDS) is submitted on 9/10/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Memory power control by enable circuit that operates in response to decrease of a voltage signal. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12119040 (Reference Application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare independent claim 1, 6 and 7 of Instant Application with independent claim 1 of Reference Application as shown below, we find that same claim limitations are recited in both Applications. Instant Application USP’ 12119040 1. A device, comprising: a plurality of first switches connected in series; the plurality of first switches including a first switch, wherein a first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain; a second switch, a first terminal of the second switch configured to receive a second voltage signal in a second voltage domain different from the first voltage domain, wherein a second terminal of the second switch coupled to and a second terminal of the first switch are both coupled together and connected to a voltage output terminal; and a control circuit configured to turn on at least one of the first switches in response to a decrease of the voltage level of the first voltage signal. 6. (New) The device of claim 1, wherein the control circuit includes an enable input terminal configured to receive an enable signal, wherein the enable signal is based on the voltage level of the first voltage signal. 7. (New) The device of claim 6, wherein the enable circuit includes an input terminal configured to receive the first voltage signal in the first voltage domain and an output terminal configured to output the enable signal to the enable input terminal. 1. A device, comprising: a first switch, a first terminal of the first switch configured to receive a first voltage signal in a first voltage domain; a second switch, a first terminal of the second switch configured to receive a second voltage signal in a second voltage domain different from the first voltage domain, a second terminal of the second switch coupled to a second terminal of the first switch; a control circuit coupled to control terminals of the first switch and the second switch, and configured to turn on the first switch in response to a decrease of a voltage level of the first voltage signal, wherein the control circuit includes an enable input terminal configured to receive an enable signal, and wherein the enable signal is based on the voltage level of the first voltage signal; and an enable circuit having an input terminal configured to receive the first voltage signal in the first voltage domain and an output terminal configured to output the enable signal to the enable input terminal. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Shin (US 20200119723) --- it teaches two voltage domain but output from one domain is input to other domain which contradicts Instant Application. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571272 1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SULTANA BEGUM/Primary Examiner, Art Unit 2824 3/9/2026
Read full office action

Prosecution Timeline

Jul 25, 2024
Application Filed
Mar 26, 2025
Response after Non-Final Action
Mar 09, 2026
Non-Final Rejection — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603121
MEMORY REFRESH WITH NEGATIVE VOLTAGE GENERATOR
2y 5m to grant Granted Apr 14, 2026
Patent 12597457
INITIAL SETTING DEVICE OF SEMICONDUCTOR MEMORY TO DETERMINE VALID SETTING
2y 5m to grant Granted Apr 07, 2026
Patent 12592276
SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER THAT OPERATES FOR TWO DIFFERENT VOLTAGE RANGE AND WRITING METHOD THEREOF
2y 5m to grant Granted Mar 31, 2026
Patent 12592272
MEMORY DEVICE HAVING NON-UNIFORM REFRESH
2y 5m to grant Granted Mar 31, 2026
Patent 12580008
POWER GATING CIRCUIT WITH MEMORY PRECHARGE SUPPORT
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
94%
With Interview (+0.4%)
1y 11m
Median Time to Grant
Low
PTA Risk
Based on 522 resolved cases by this examiner. Grant probability derived from career allow rate.

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