Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the application filed July 25, 2024.
Claims 1-20 are pending.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. This application is a divisional application of prior-filed U.S. application No. 17/461,668, filed on 30 August, 2021, and issued as U.S. Patent No. 12,293,970 on May 6, 2025.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on November 26, 2024 and January 22, 2025 have been placed in the application file and are being considered by the examiner.
Drawings
The drawings filed with the application on July 25, 2024 are accepted.
Claim Objections
Claims 11, 12, 16, and 17 are objected to because of the following informalities: various spelling mistakes. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 6 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 6 recites the limitation "wherein at least a trench is entirely filled". There is insufficient antecedent basis for this limitation in the claim. For examination purposes, this limitation will be interpreted as “wherein at least one of the plurality of trenches is entirely filled”. Support for this interpretation is available at, for example, FIG. 19 and associated text of Applicant’s disclosure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al., US 2019/0206725 A1 (hereinafter Chu).
Regarding claim 11, Chu discloses: A method for manufacturing a semiconductor structure, the method comprising: forming a hard mask layer over a dielectric layer (Chu, FIGs. 1A, 1B show hardmask layer 140 [the hard mask layer] formed over insulating layer 130 [the dielectric layer], [0037-0038]), the dielectric layer is over a substrate (Chu, FIGs. 1A, 1B, substrate 110, [0032-0033]);
forming a plurality of mandrels over the hard mask layer (Chu, FIGs. 1A, 1B show “pattern of sacrificial mandrels 150 [the plurality of mandrels] formed on [over] the hardmask layer 140 [the hard mask layer],” [0032]);
forming a spacer layer between the mandrels (Chu, FIG. 2 shows spacer material 160A [the spacer layer] on and between the mandrels 150 [the mandrels], [0044]);
forming a first opening and a second opening over the hard mask layer (Chu, FIGs. 3A-4A, gap G1 [the first opening] and gap G2 [the second opening], [0043-0045]), wherein the first opening is located between two adjecent [sic] mandrels (Chu, FIGs. 3A-4A show gap G1 [the first opening] located between two adjacent mandrels 150 [two adjacent mandrels]), and the second opening is formed by removing a portion of one of the mandrels (Chu, FIGs. 3A-4A show gap G2 [the second opening] is formed by removing a portion of one of mandrels 150 [one of the mandrels], “the gaps G2 [the second opening] represent the spaces that are formed after removing the sacrificial mandrels 150 [the mandrels],” [0045]);
etching the hard mask layer through the first opening and the second opening (Chu, see FIGs. 4A-6A, portions of the hardmask layer 140 [the hard mask layer] exposed by gaps G1 [the first opening and gaps G2 [the second opening] are etched down to the insulating layer 130 [the dielectric layer], [0048]);
patterning the dielectric layer through the hard mask layer (Chu, FIG. 10 shows “patterning the insulating layer 130 [the dielectric layer] using the patterned hardmask layer 140 [the hard mask layer] as an etch hardmask,” [0052]); and
forming a plurality of conductive lines in the patterned dielectric layer (Chu, FIGs. 11A, 11B, metal lines 180 [the plurality of conductive lines] shown in patterned insulating layer 130 [the patterned dielectric layer], [0053]).
Regarding claim 12, Chu discloses: The method of claim 11, wherein the spacer layer comprises a plurality of trenches substaintially [sic] parallel to each other (Chu, FIGs. 2-3B show spacer material 160/160A [the spacer layer] comprises a plurality of trenches parallel to each other and to the mandrels 150 [the mandrels], [0039; 0044]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7, 9, 10, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al., US 2019/0206725 A1 (hereinafter Chu) in view of Kim, U.S. Pat. No. 9,941,164 B1 (hereinafter Kim).
Regarding claim 1, Chu discloses: A method for manufacturing a semiconductor structure, the method comprising: forming a hard mask layer over a dielectric layer (Chu, FIGs. 1A, 1B show hardmask layer 140 [the hard mask layer] formed over insulating layer 130 [the dielectric layer], [0037-0038]), the dielectric layer is over a substrate (Chu, FIGs. 1A, 1B, substrate 110, [0032-0033]);
forming a plurality of mandrels over the hard mask layer (Chu, FIGs. 1A, 1B show “pattern of sacrificial mandrels 150 [the plurality of mandrels] formed on [over] the hardmask layer 140 [the hard mask layer],” [0032]);
forming a spacer layer over the hard mask layer and the mandrels (Chu, FIG. 2 shows spacer material 160A [the spacer layer] over hardmask layer 140 [the hard mask layer] and mandrels 150 [the mandrels], [0042]), the spacer layer comprises a plurality of trenches between the mandrels (Chu, FIG. 2 shows spacer material 160A [the spacer layer] comprises a plurality of trenches between the mandrels 150 [the mandrels], [0044]);
forming at least a first opening in the spacer layer (Chu, FIG. 3A shows gap G1 [the first opening] formed in spacer material layer 160A [the spacer layer], [0043-0044]);
forming at least a second opening by removing a portion of the mandrels (Chu, FIGs. 3A, 4A show forming gap G2 [the second opening] by etching, i.e., removing mandrels 150 [the mandrels], [0045]);
etching the hard mask layer through the first opening and the second opening (Chu, see FIGs. 4A-6A, portions of the hardmask layer 140 [the hard mask layer] exposed by gaps G1 [the first opening and gaps G2 [the second opening] are etched down to the insulating layer 130 [the dielectric layer], [0048]);
patterning the dielectric layer through the hard mask layer (Chu, FIG. 10 shows “patterning the insulating layer 130 [the dielectric layer] using the patterned hardmask layer 140 [the hard mask layer] as an etch hardmask,” [0052]); and
forming a plurality of conductive lines in the patterned dielectric layer (Chu, FIGs. 11A, 11B, metal lines 180 [the plurality of conductive lines] shown in patterned insulating layer 130 [the patterned dielectric layer], [0053].
Chu is silent regarding: filling a first portion of the trenches by a first block material; filling a second portion of the trenches by a second block material after filling the first portion of the trenches by a first block material, wherein a third portion of the trenches are free from being filled by the first block material and the second block material.
However, Kim, in the same field of endeavor, teaches: filling a first portion of the trenches by a first block material (Kim, FIG. 4, first block patterns 40, “the first block pattern 40 is shown to overlap the gap between two spaces (space area 32) [the first portion of the trenches],” col. 7, line 50 – col. 8, line 12);
filling a second portion of the trenches by a second block material after filling the first portion of the trenches by a first block material (Kim, FIG. 5, second block patterns 60, “the second block pattern 60 may extend in the first direction (X-direction) to overlap the … two gaps each between two spacers (space areas 33) [the second portion of the trenches],” col. 8, line 60 – col. 9, line 22), wherein a third portion of the trenches are free from being filled by the first block material and the second block material (Kim, FIGs. 4 and 5 show the third portion of the trenches as the space areas 32 and 33 that are not filled by either of first block patterns 40 [the first block pattern] or second block patterns 60 [the second block pattern]);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chu with the teachings of Kim, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kim to provide a block mask layout with reduced defect levels (Kim, col. 4, lines 6-15), thereby improving manufacturing yield.
Regarding claim 5, Chu in view of Kim teaches: The method of claim 1, wherein a width of the second portion of the trench is greater than a width of the first portion of the trench (Kim, see FIGs. 4, 5, col. 8, line 60-col. 9, line 22). Kim teaches that the width of each of the first block pattern 40 [the first block pattern], and the underlying first portion of the trench, and the second block patterns 60 [the second block patterns], and the underlying second portion of the trench, may be chosen as needed in order to avoid overlay concerns (Kim, col. 9, lines 10-22).
Regarding claim 6, insofar as the claim can be understood in view of the 35 USC 112 rejections or claim objections above, Chu in view of Kim teaches: The method of claim 1, wherein at least [[a trench]] one of the plurality of trenches is entirely filled by the second block material. (Chu, FIG. 5A shows leftmost trench, i.e., one of the plurality of trenches, entirely filled with block mask 165, [0047]).
Regarding claim 7, Chu in view of Kim teaches: The method of claim 1, wherein the hard mask layer comprises titanium, tantalum, titanium nitride (Chu, hardmask layer 140 [the hard mask layer] “formed of a nitride material such as TiN,” [0038]) or tantalum nitride.
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Chu include one or more of Applicant’s claimed alternative elements, for example: titanium nitride.
Regarding claim 9, Chu in view of Kim teaches: The method of claim 1, wherein forming the first opening in the spacer layer comprises etching a bottom of at least one of the trenches to expose the hard mask layer (Chu, FIGs. 2-3A show forming of gap G1 [the first opening] in trenches of spacer material layer 160A [the spacer layer] “using a directional dry etch process,” exposing upper surface of hard mask layer 140 [the hard mask layer] in the gap G1 [the first opening], [0043-0044]).
Regarding claim 10, Chu in view of Kim teaches: The method of claim 1, wherein a depth of each of the trenches between the mandrels in forming the spacer layer is substantially the same (Chu, FIG. 2 shows depth of trenches between the mandrels 150 [the mandrels] in forming spacer material 160A [the spacer layer] is substantially the same, and the depth of each of the trenches is equal to the height of the mandrels 150 [the mandrels], [0044]).
Regarding claim 13, Chu discloses: The method of claim 12, wherein forming the first opening over the hard mask layer (Chu, FIGs. 3A-4A, gap G1 [the first opening] over hardmask layer 140 [the hard mask layer]) … etching a bottom of at least one of the trenches to expose the hard mask layer (Chu, FIGs. 2-3A show forming of gap G1 [the first opening] in trenches of spacer material layer 160A [the spacer layer] “using a directional dry etch process,” exposing upper surface of hard mask layer 140 [the hard mask layer] in the gap G1 [the first opening], [0043-0044]).
Chu is silent regarding: filling a first portion of the trenches by a first block material; filling a second portion of the trenches by a second block material after filling the first portion of the trenches by a first block material, wherein a third portion of the trenches are free from being filled by the first block material and the second block material.
However, Kim, in the same field of endeavor, teaches: filling a first portion of the trenches by a first block material (Kim, FIG. 4, first block patterns 40, “the first block pattern 40 is shown to overlap the gap between two spaces (space area 32) [the first portion of the trenches], col. 7, line 50 – col. 8, line 12);
filling a second portion of the trenches by a second block material after filling the first portion of the trenches by a first block material (Kim, FIG. 5, second block patterns 60, col. 8, line 60 – col. 9, line 22), wherein a third portion of the trenches are free from being filled by the first block material and the second block material (Kim, FIGs. 4 and 5 show the third portion of the trenches as the space areas 32 and 33 that are not filled by either of first block patterns 40 [the first block pattern] or second block patterns 60 [the second block pattern]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chu with the teachings of Kim, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kim to provide a block mask layout with reduced defect levels (Kim, col. 4, lines 6-15), thereby improving manufacturing yield.
Regarding claim 14, Chu in view of Kim teaches: The method of claim 13. Chu in view of Kim teaches that a material of the hard mask layer is selected to provide etch selectivity (Chu, hardmask layer 140 [the hard mask layer] comprises “a nitride material such as TiN or SiN, etc.” [0038]). Kim teaches that the block material is selected to provide etch selectivity between different patterning stack materials (Kim, col. 2, lines 1-48). Therefore, although Chu in view of Kim does not explicitly teach that a material of the hard mask layer is identical to the first block material, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Chu and Kim, insofar as selecting an appropriate material for each of the hard mask layer and the first block material, and in pursuing the known limited number of options, i.e., each material is the same, or each material is different, with a reasonable expectation of success. The motivation for doing so would be, as recognized by Kim, to select hard mask and block materials with appropriate etch selectivity for the manufacturing process.
Claims 2, 3, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Chu in view of Kim and further in view of Lin et al., US 2020/0258754 A1 (hereinafter Lin).
Regarding claim 2, Chu in view of Kim teaches: The method of claim 1. Chu in view of Kim is silent regarding: forming a first bottom layer over the spacer layer; and patterning the first bottom layer to expose the first portion of the trenches prior to filling the first portion of the trenches by the first block material.
However, Lin, in the same field of endeavor, teaches: forming a first bottom layer over the spacer layer (Lin, FIG. 6A shows bottom layer 128 [the first bottom layer] over spacer layer 126 [the spacer layer], [0031]); and patterning the first bottom layer to expose the first portion of the trenches prior to filling the first portion of the trenches by the first block material (Lin, FIG. 7A shows trenches exposed by openings 136A and 136B resulting from patterning the bottom layer 128 [the first bottom layer], [0032-0033]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chu in view of Kim with the teachings of Lin, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Lin, to improve pattern-transferring performance to attain smaller pitch spacing (Lin, [0009; 0026]), thereby improving manufacturing yield and device performance and reliability.
Regarding claim 3, Chu in view of Kim and further in view of Lin teaches: The method of claim 1, further comprising: forming a second bottom layer over the spacer layer and the first block material (Lin, FIG. 6A shows middle layer 130 [the second bottom layer] over spacer layer 126 [the spacer layer], [0031]); and patterning the second bottom layer to expose the second portion of the trenches prior to filling the second portion of the trenches by the second block material (Lin, FIG. 7A shows trenches exposed by openings 136A and 136B resulting from patterning the middle layer 130 [the second bottom layer], [0032-0033]).
Additionally, absent a showing of new or unexpected results, mere duplication of parts, as with Applicant’s claimed second bottom layer, is a common practice requiring only ordinary skill in the art and has no patentable significance absent a showing of new and unexpected results, see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP 2144.
Regarding claim 4, Chu in view of Kim and further in view of Lin teaches: The method of claim 1, further comprising: forming a third bottom layer over the spacer layer (Lin, FIG. 6A shows upper layer 132 [the third bottom layer] over spacer layer 126 [the spacer layer], [0031]), the first block material and the second block material; and patterning the third bottom layer to remove a portion of the third bottom layer and the portion of the mandrels (Lin, FIG. 7A shows trenches exposed by openings 136A and 136B resulting from patterning the upper layer 132 [the third bottom layer], [0032-0033]).
Additionally, absent a showing of new or unexpected results, mere duplication of parts, as with Applicant’s claimed third bottom layer, is a common practice requiring only ordinary skill in the art and has no patentable significance absent a showing of new and unexpected results, see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP 2144.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chu in view of Kim and further in view of Li et al., US 2020/0104450 A1 (hereinafter Li).
Regarding claim 8, Chu in view of Kim teaches: The method of claim 1. However, Chu in view of Kim is silent regarding: wherein each of the trenches between the mandrels is located between a power rail region and a ground rail region parallel to the power rail region.
However, Li, in the same field of endeavor, teaches that it was known in the art before the effective filing date of the claimed invention to provide an integrated circuit with “a plurality of first power rails held at a source voltage potential (VDD) [power rail region] and a plurality of second power rails held at a ground voltage potential (VSS) [ground rail region],” (Li, [0018]) and that “The layout also includes routing tracks for routing of signal lines and power rails for connections within the cell and between other cells. The routing track run parallel to one another across the cell,” (Li, [0025]; FIG. 2 shows the layout of signal lines and power rails, analogous to the layout of trenches and mandrels as taught by Chu in view of Kim, [0035-0036]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chu in view of Kim with the teachings of Li, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Li, to provide “at least one power supply and at least one reference voltage to connect to elements within the cell,” (Li, [0026]), thereby enabling device functionality.
Claim 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chu in view of Li.
Regarding claim 15, Chu discloses: The method of claim 11, including the plurality of conductive lines (Chu, FIGs. 11A, 11B, metal lines 180 [the plurality of conductive lines] shown in patterned insulating layer 130 [the patterned dielectric layer], [0053]). Chu does not explicitly teach that the plurality of conductive lines are located between a power rail and a ground rail parallel to the power rail, and each of the conductive lines is parallel to the power rail.
However, Li, in the same field of endeavor, teaches that it was known in the art before the effective filing date of the claimed invention to provide an integrated circuit with “a plurality of first power rails held at a source voltage potential (VDD) [power rail region] and a plurality of second power rails held at a ground voltage potential (VSS) [ground rail region],” (Li, [0018]) and that “The layout also includes routing tracks for routing of signal lines [the plurality of conductive lines] and power rails for connections within the cell and between other cells. The routing track run parallel to one another across the cell,” (Li, [0025]; FIG. 2 shows the layout of signal lines and power rails, analogous to the layout of the plurality of conductive lines, as taught by Chu, [0035-0036]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chu with the teachings of Li, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Li, to provide “at least one power supply and at least one reference voltage to connect to elements within the cell,” (Li, [0026]), thereby enabling device functionality.
Regarding claim 16, Chu teaches: A method for manufacturing a semiconductor structure, the method comprising: receiving a substrate (Chu, FIGs. 1A, 1B, substrate 110, [0032-0033])
forming a dielectric layer over the substrate (Chu, FIGs. 1A, 1B, insulating layer 130 [the dielectric layer] formed over substrate 110, [0032]);
forming a hard mask layer over the over a dielectric layer (Chu, FIGs. 1A, 1B show hardmask layer 140 [the hard mask layer] formed over insulating layer 130 [the dielectric layer], [0037-0038])
forming a plurality of mandrels over the hard mask layer (Chu, FIGs. 1A, 1B show “pattern of sacrificial mandrels 150 [the plurality of mandrels] formed on [over] the hardmask layer 140 [the hard mask layer],” [0032]);
forming a spacer layer over the hard mask layer and the mandrels (Chu, FIG. 2 shows spacer material 160A [the spacer layer] over hardmask layer 140 [the hard mask layer] and mandrels 150 [the mandrels], [0042]), the spacer layer comprises a plurality of trenches between the mandrels (Chu, FIG. 2 shows spacer material 160A [the spacer layer] comprises a plurality of trenches between the mandrels 150 [the mandrels], [0044]);
forming at least a first opening and at least a second opening over the hard mask layer (Chu, FIGs. 3A-4A, gap G1 [the first opening] and gap G2 [the second opening], [0043-0045]), wherein the first opening is formed by etching a bottom of at least one of the trenches to expose the hard mask layer (Chu, FIGs. 2-3A show forming of gap G1 [the first opening] in trenches of spacer material layer 160A [the spacer layer] “using a directional dry etch process,” exposing upper surface of hard mask layer 140 [the hard mask layer] in the gap G1 [the first opening], [0043-0044]), and the second opening is formed by removing a portion of one of the mandrels (Chu, FIGs. 3A-4A show gap G2 [the second opening] is formed by removing a portion of one of mandrels 150 [one of the mandrels], “the gaps G2 [the second opening] represent the spaces that are formed after removing the sacrificial mandrels 150 [the mandrels],” [0045]);
etching the hard mask layer through the first opening and the second opening (Chu, see FIGs. 4A-6A, portions of the hardmask layer 140 [the hard mask layer] exposed by gaps G1 [the first opening and gaps G2 [the second opening] are etched down to the insulating layer 130 [the dielectric layer], [0048]);
patterning the dielectric layer through the hard mask layer (Chu, FIG. 10 shows “patterning the insulating layer 130 [the dielectric layer] using the patterned hardmask layer 140 [the hard mask layer] as an etch hardmask,” [0052]); and
forming a plurality of conductive lines in the patterned dielectric layer (Chu, FIGs. 11A, 11B, metal lines 180 [the plurality of conductive lines] shown in patterned insulating layer 130 [the patterned dielectric layer], [0053].
Chu is silent regarding: a power rail region and a ground rail region parallel to the power rail region from a top view perspective [sic] … forming a hard mask layer at least between the power rail region and a ground rail region.
However, Chu teaches that it was known in the art to use a hardmask layer during the manufacturing process to pattern parallel trenches to form metal lines such as power rails, (Chu, [0003-0005]). Li, in the same field of endeavor, teaches that it was known in the art before the effective filing date of the claimed invention to provide an integrated circuit with “a plurality of first power rails held at a source voltage potential (VDD) [a power rail region] and a plurality of second power rails held at a ground voltage potential (VSS) [a ground rail region],” (Li, [0018]) and that “The layout also includes routing tracks for routing of signal lines and power rails for connections within the cell and between other cells. The routing track run parallel to one another across the cell,” (Li, [0025]; FIG. 2 shows a top view perspective of the layout of parallel power rail and ground rail regions, [0035-0036]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chu with the teachings of Li, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Li, to provide “at least one power supply and at least one reference voltage to connect to elements within the cell,” (Li, [0026]), thereby enabling device functionality.
Regarding claim 17, Chu in view of Li teaches: The method of claim 16, wherein the plurality of conductive lines are arranged in a first row and a second row parallel to the first row (Li, FIG. 4B shows routing tracks 210a [the plurality of conductive lines] arranged in a first row, shown with dark outline, and a second row parallel to the first row, shown without dark outline, [0041-0043]), the first row and the second row are located between the power rail region and the ground rail region (Li, FIG. 4B shows routing tracks 210a [the plurality of conductive lines] located between routing tracks 210b, power rail VDD and power rail VSS [the power rail region and the ground rail region], [0041-0043]), wherein a distance between two adjecent [sic] conductive lines in the first row is different from a distance between two adjacent conductive lines in the second row (Li, FIG. 4B shows distance between two adjacent routing tracks 210a shown with dark outline [the conductive lines in the first row] is different from a distance between two adjacent routing tracks 210a shown without dark outline [the conductive lines in the second row], [0041-0043]).
Regarding claim 18, Chu in view of Li teaches: The method of claim 17, further comprising: forming a plurality of vias in contact with the conductive lines in the first row (Chu, FIG. 1A, BEOL structure including conductive vias, [0036]; Li, FIGs. 5A-5B, vias 530, [0047]), wherein the each of the vias is in contact with an end of one of the conductive lines in the first row (Li, FIGs. 5A-5B, each of vias 530 [the plurality of vias] shown in contact with an end of conductive lines 520, i.e., the conductive lines in the first row).
Regarding claim 19, Chu in view of Li teaches: The method of claim 18, wherein at least a portion of the plurality of vias are formed prior to forming the conductive lines (Chu, FIG. 1A, FEOL/MOL structure 120 including via contacts shown formed prior to forming metal lines 180 [the plurality of conductive lines], [0035-0036; 0053]).
Regarding claim 20, Chu in view of Li teaches: The method of claim 16, wherein a distance between two adjacent second openings (Chu, FIG. 9A, width W [the second openings], [0051; 0058-0059]) is greater than a distance between one of the first opening and one of the second opening from a cross-sectional view perspective (Chu, FIG. 9A shows gap between adjacent widths W [the second openings], shown on either side of width W2 [the first opening], is greater than a distance between width W2 [the first opening] and the width W next to width W2 [one of the second opening] from a cross-sectional view perspective).
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. The cited prior art discloses similar materials, devices, and methods.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights