DETAILED ACTION
This Action is responsive to the communication filed on 07/25/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Terms and phrases used in the claims presented in the application should find antecedent basis in the description so that the meaning of the terms in the claims may be ascertainable by reference to the description. Correction of the following is required: The claimed limitation recited as “via bar” does not have antecedent basis in the specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation is claim 14 recited as: “the first portions of the second metal line have a first thickness and the second portions of the second metal line have a second thickness that is less than the first thickness” (emphasis added) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 14 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 14, which depends from Claim 1, recites the following limitation: “the second metal line has first portions disposed on the MTJ devices and second portions disposed on insulation regions between the MTJ devices, wherein the first portions of the second metal line have a first thickness and the second portions of the second metal line have a second thickness that is less than the first thickness” (emphasis added). However, the specification, at paragraph 0033, recites: “portions of the slot via 260A that are directly above the MTJ 150 have a thickness d2, and portions of the slot via 260A that are laterally between two adjacent MTJs 150 have a thickness d3. In some embodiments, the thickness d3 is equal to or greater than the thickness d2” (emphasis added). Therefore, the claim fails to comply with the written description because the contains subject matter which was not described in the specification.
Claims 17-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 17 recites the limitation: “a first layer of an interconnect structure that includes a via bar in a first region and a via in a second region” (emphasis added). The written description fails to comply with the written description requirement because the written description fails to describe “a first layer of an interconnect structure that includes a via bar in a first region.”
Claims 18-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement due to the claims’ dependency to Claim 17.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6, 10-13, and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang (US 2021/0074907).
Regarding claim 1, Wang (see, e.g., FIG. 10) discloses a semiconductor structure comprising:
a first metal layer 24, 26 (Para 0012);
a second metal layer 62, 72, 76, 78, 80, 100, 102 disposed over the first metal layer 24, 26, wherein the second metal layer 62, 72, 76, 78, 80, 100, 102 includes multiple magnetic tunneling junction (MTJ) devices 62, 76, 78; 72, 76, 78 in a memory device region 14 and a first conductive feature 102 in a logic device region 16, wherein each of the MTJ devices 62, 76, 78; 72, 76, 78 includes a bottom electrode 76 and an MTJ stack 62, 72 disposed over the bottom electrode 76 (Para 0016, Para 0023-Para 0028); and
a third metal layer 106, 110 disposed immediately above the second metal layer 62, 72, 76, 78, 80, 100, 102, wherein the third metal layer 106, 110 includes a first via 110 (in logic region 16, bottom portion) disposed over and electrically connecting to the first conductive feature 102, and a slot via 110 (in MTJ region 14, bottom portion) disposed over the MTJ devices 62, 76, 78; 72, 76, 78 and electrically connecting to the MTJ stack 62, 72 of each of the MTJ devices 62, 76, 78; 72, 76, 78,
wherein:
the slot via 110 (in MTJ region 14, bottom portion) occupies a space e.g., space between 62, 76, 78 and 72, 76, 78 extending continuously and laterally from a first one 62, 76, 78 of the MTJ devices 62, 76, 78; 72, 76, 78 to a last one 72, 76, 78 of the MTJ devices 62, 76, 78; 72, 76, 78,
a first thickness e.g., thickness of 110 (in logic region 16, bottom portion) of the first via 110 (in logic region 16, bottom portion) is equal to or less than a second thickness e.g., thickness of 110 (in MTJ region 14, bottom portion) of the slot via 110 (in MTJ region 14, bottom portion) directly above the MTJ stack e.g., 62 of one of the MTJ devices 62, 76, 78,
the third metal layer 106, 110 further includes a second conductive feature 110 (in logic region 16, top portion) disposed over and electrically connecting to the first via 110 (in logic region 16, bottom portion), and a third conductive feature 110 (in MTJ region 14, top portion) disposed over and electrically connecting to the slot via 110 (in MTJ region 14, bottom portion) (Para 0024).
Regarding claim 2, Wang (see, e.g., FIG. 10) teaches the semiconductor structure of claim 1, wherein both the slot via 110 (in MTJ region 14, bottom portion) and the first via 110 (in logic region 16, bottom portion) include copper (Para 0024).
Regarding claim 3, Wang (see, e.g., FIG. 10) teaches the semiconductor structure of claim 2, wherein both the second conductive feature 110 (in logic region 16, top portion) and the third conductive feature 110 (in MTJ region 14, top portion) include copper (Para 0024).
Regarding claim 6, Wang (see, e.g., FIG. 10) teaches the semiconductor structure of claim 1, wherein one e.g., 62, 76, 78 of the MTJ devices 62, 76, 78; 72, 76, 78 further includes a top electrode 78 vertically between the slot via 110 (in MTJ region 14, bottom portion) and the MTJ stack e.g., 62 of the one e.g., 62, 76, 78 of the MTJ devices 62, 76, 78; 72, 76, 78 (Para 0016).
Regarding claim 10, Wang (see, e.g., FIG. 10) discloses a device structure comprising:
a first level of an interconnect structure 62, 76, 78; 72, 76, 78; 118, 120 that includes a group of magnetic tunneling junction (MTJ) devices 62, 76, 78; 72, 76, 78 in a first region 14 and a first interconnect stack 118, 120 in the second region 16, wherein the interconnect stack 118, 120 includes a first metal line 120 disposed over a first metal via 118 (Para 0016, Para 0023-Para 0028); and
a second level of the interconnect structure 110 (top portion in region 14), 110 (bottom portion in region 14), 110 (top portion in region 16), 110 (bottom portion in region 16) disposed on the first level of the interconnect structure 62, 76, 78; 72, 76, 78; 118, 120, wherein the second level of the interconnect structure 110 (top portion in region 14), 110 (bottom portion in region 14), 110 (top portion in region 16), 110 (bottom portion in region 16) includes a second interconnect stack 110 (top portion in region 14), 110 (bottom portion in region 14) in the first region 14 and a third interconnect stack 110 (top portion in region 16), 110 (bottom portion in region 16) in the second region 16 (Para 0024),
wherein:
the second interconnect stack 110 (top portion in region 14), 110 (bottom portion in region 14) includes a second metal line 110 (bottom portion in region 14) and a third metal line 110 (top portion in region 14), wherein the second metal line is disposed on each MTJ device 62, 76, 78 and 72, 76, 78 of the group of MTJ devices 62, 76, 78; 72, 76, 78 and the third metal line 110 (top portion in region 14) is disposed on the second metal line 110 (bottom portion in region 14), and
the third interconnect stack 110 (top portion in region 16), 110 (bottom portion in region 16) includes a fourth metal line 110 (top portion in region 16) and a second metal via 110 (bottom portion in region 16), wherein the second metal via 110 (bottom portion in region 16) is disposed on the first metal line 120 and the fourth metal line 110 (top portion in region 16) is disposed on the second metal via 110 (bottom portion in region 16).
Regarding claim 11, Wang (see, e.g., FIG. 10) teaches the device structure of claim 10, wherein the first region 14 abuts the second region 16 (Para 0010).
Regarding claim 12, Wang (see, e.g., FIG. 10) teaches the device structure of claim 10, wherein: the first region 14 is a memory region (Para 0010); and the second region 16 is a logic region (Para 0010).
Regarding claim 13, Wang (see, e.g., FIG. 10) teaches the device structure of claim 10, wherein a first thickness e.g., thickness of 110 (bottom portion in region 14) of the second metal line 110 (bottom portion in region 14) is the same as a second thickness e.g., thickness of 110 (bottom portion in region 16) of the second metal via 110 (bottom portion in region 16).
Regarding claim 15, Wang (see, e.g., FIG. 10) teaches the device structure of claim 10, wherein a first length e.g., length of 110 (top portion in region 14) of the third metal line 110 (top portion in region 14) is greater than a second length e.g., length of 110 (bottom portion in region 14) of the second metal line 110 (bottom portion in region 14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2021/0074907), in view of Chuang (US 2017/0194557).
Regarding claim 7, Wang (see, e.g., FIG. 10) teaches the semiconductor structure of claim 1, wherein each of the MTJ devices 62, 76, 78; 72, 76, 78 further includes a spacer 68 on sidewalls of the MTJ stack 62 and 72 of the respective MTJ device 62, 76, 78 and 72, 76, 78 (Para 0025).
Although Wang shows substantial features of the claimed invention, Wang fails to expressly teach a protection layer on sidewalls of the spacer, wherein a portion of the slot via is disposed in a space laterally between the protection layer of two adjacent ones of the MTJ devices.
Chuang (see, e.g., FIG. 23) teaches a protection layer 127 on sidewalls of the spacer 143 for the purpose of preventing oxidation and other contamination (Para 0026-Para 0027, Para 0044).
The combination of Wang (see, e.g., FIG. 10) / Chuang (see, e.g., FIG. 23) teaches a portion e.g., center portion connecting left and right 110 vias (in MTJ region 14) (as taught by Wang) of the slot via 110 (in MTJ region 14, bottom portion) (as taught by Wang) is disposed in a space e.g., space between 62, 76, 78; 72, 76, 78 between laterally between the protection layer 127 (as taught by Chuang) of two adjacent ones 62, 76, 78 and 72, 76, 78 (as taught by Wang) of the MTJ devices 62, 76, 78; 72, 76, 78 (as taught by Wang).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the protection layer as described by Chuang to the sidewalls of the spacers in the device of Wang for the purpose of preventing oxidation and other contamination (Para 0044).
Regarding claim 8, Wang (see, e.g., FIG. 10) teaches the semiconductor structure of claim 7, wherein a bottom surface e.g., bottom surface of center portion connecting left and right 110 vias (in MTJ region 14) of the portion e.g., center portion connecting left and right 110 vias (in MTJ region 14) of the slot via 110 (in MTJ region 14, bottom portion) is substantially flat.
Allowable Subject Matter
Claims 4-5, 9, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571)270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Prosecution Insights