DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 5, the claim recites, “a first depth of the first layer relative to a center of the source/drain region, at a height of the third nanostructure channel, is greater relative to a second depth of the first layer relative to the center of the source/drain region at a height of the second nanostructure channel”, which does not have support in the disclosure. The specification and Figure 6 show the first epitaxial source/drain layer 504 adjacent the second nanostructure channel 208b and the third nanostructure channel 208c. As shown, the first layer 504 extends farther toward the center of the source/drain region at the height of the third nanostructure channel 208c than at the height of the second nanostructure channel 208b. Accordingly, the illustrated depth associated with the second nanostructure channel 208b (D2) is greater than the depth associated with the third nanostructure channel 208c (D1) that is, D2>D1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10-11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US 2020/0381546 A1; hereafter Cho).
Regarding claim 10, Cho teaches a semiconductor device (see e.g., semiconductor device of Figures 3, 35), comprising:
a first plurality of nanostructure channels arranged in a direction that is approximately perpendicular to a substrate of a semiconductor device (see e.g., a first plurality of semiconductor patterns 132a vertically stacked above the substrate 100 and serves as multichannel regions of the transistor, Paras [0027], [0030], Figure 35);
a second plurality of nanostructure channels arranged in the direction that is approximately perpendicular to the substrate of the semiconductor device (see e.g., a second plurality of semiconductor patterns 132a vertically stacked above the substrate 100 and serves as multichannel regions of the transistor, Paras [0027], [0030], Figure 35);
a source/drain region laterally between the first plurality of nanostructure channels and the second plurality of nanostructure channels (see e.g., source/drain region 150/152 laterally between the first and second plurality of semiconductor patterns 132a, Para [0053], [0059], Figure 35),
a first plurality of inner spacers laterally adjacent to the source/drain region and vertically alternating with ends of the first plurality of nanostructure channels; and (see e.g., a first plurality of inner spacers 144 laterally adjacent to the source/drain 150/152 and vertically alternating with ends of the first plurality of semiconductor patterns 132a, Para [0043], Figure 35)
a second plurality of inner spacers laterally adjacent to the source/drain region and vertically alternating with ends of the second plurality of nanostructure channels (see e.g., a second plurality of inner spacers 144 laterally adjacent to the source/drain 150/152 and vertically alternating with ends of the second plurality of semiconductor patterns 132a, Para [0043], Figure 35),
wherein the source/drain region comprises:
a first doped semiconductor layer continuously extending along the ends of the first plurality of nanostructure channels, the first plurality of inner spacers, the ends of the second plurality of nanostructure channels, and the second plurality of inner spacers; and (see e.g., The first semiconductor layer 150 may contact the sidewalls of the semiconductor patterns 132a and the first spacers 144 and the upper surface of the active region 100a. The first semiconductor layer 150 may have a connected shape, and be continuously formed (i.e., to have a continuously connected shape), along the sidewalls of the semiconductor patterns 132a and the first spacers 144 and the upper surface of the active region 100a, Para [0053], Figure 35)
a second doped semiconductor layer on the first doped semiconductor layer (see e.g., second semiconductor layer 152 formed on the first semiconductor layer 150, Para [0059], Figure 35),
wherein a dopant concentration in the second doped semiconductor layer is greater than a dopant concentration in the first doped semiconductor layer (see e.g., the second semiconductor layer 152 is doped with second impurities to have a second impurity concentration. The first semiconductor layer 150 is doped with first impurities to have a first impurity concentration. The second impurity concentration is higher than the first impurity concentration, Para [0059], Figure 35).
Regarding claim 11, Cho, as modified, in claim 10 further teaches
wherein the first doped semiconductor layer has an approximate U-shaped cross-sectional profile (see e.g., the first semiconductor layer 150 has a U-shaped ross-sectional profile, Figures 3 and 35).
Regarding claim 13, Cho, as modified, in claim 10 further teaches
wherein a height of a top surface of the second doped semiconductor layer is greater than a height of a top surface of a top-most channel of the first plurality of nanostructure channels (see e.g., The height of a top surface of the second semiconductor layer 152 is greater than a height of a top surface of a top most semiconductor pattern 132a, Figures 3 and 35).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0381546 A1; hereafter Cho) in view of Chiang et al. (US 2020/0381545 A1; hereafter Chiang).
Regarding claim 1, Cho teaches a semiconductor device (see e.g., semiconductor device of Figures 3, 35), comprising:
a plurality of nanostructure channels above a portion of a fin structure (see e.g., a plurality of semiconductor patterns 132a vertically stacked above the active region 100a and serves as multichannel regions of the transistor, Paras [0027], [0030], Figure 35);
a gate structure (see e.g., gate structures 162a and 162b formed on the substrate 100, Para [0033], Figure 35),
wherein a plurality of portions of the gate structure wrap around the plurality of nanostructure channels over the portion of the fin structure (see e.g., the gate structures 162a and 162b fill gaps 158 between vertically adjacent semiconductor patterns 132a and extend around the semiconductor pattern structures, Figure 35);
a source/drain region adjacent to the plurality of nanostructure channels and adjacent to the portions of the gate structure; and (see e.g., source/drain region 150/152 adjacent to the semiconductor patterns 132a and the gate structures 162a, Paras [0053], [0059], Figure 35)
a plurality of inner spacers between the plurality of portions of the gate structure and the source/drain region (see e.g., first spacers 144 contact the sidewalls of the first gate structure 162a on an inner side and are adjacent the source/drain region 150/152, Para [0047], Figure 35),
wherein a length of at least a subset of the inner spacers is greater relative to a thickness of at least a subset of the plurality of portions of the gate structure, and (see e.g., as shown in Figure 35 the inner spacers 144 have curved inner and outer surfaces adjacent corresponding gate portions 162a wherein at least a portion of spacer 144 has a greater vertical extent than the adjacent narrowed gate portion)
Cho does not explicitly teach
“wherein the length of at least the subset of the inner spacers is lesser relative to a thickness of the plurality of nanostructure channels”.
In a similar field of endeavor Chiang teaches
wherein the length of at least the subset of the inner spacers is lesser relative to a thickness of the plurality of nanostructure channels (see e.g., Each channel layer 208 has a thickness ranging from about 6nm to about 12nm, such as 9nm. Each sacrificial layer 206, eventually removed and replaced with metal gate stack 252, has a thickness from about 2nm to about 6nm, such as 3nm. The inner spacers, including the first inner spacer layer 240 and second inner spacer layer 242, formed in the inner spacer recess 236 may have a height of 5nm to 20nm. Accordingly, dimensional ranges are disclosed encompassing for example, gate portion with a thickness of approximately 3nm, inner spacer with a vertical length of approximately 5nm and channel with a thickness of approximately 9nm thereby teaching the claimed relationship, Paras [0020], [0049], Figures 21, 22).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Chiang’s teachings of wherein the length of at least the subset of the inner spacers is lesser relative to a thickness of the plurality of nanostructure channels in the device of Cho to provide suitable dielectric isolation between gate and source/drain region while reducing parasitic capacitance and maintaining a desired channel thickness.
Regarding claim 2, Cho, as modified by Chiang, teaches the limitations of claim 1 as mentioned above. Cho does not explicitly teach
“wherein a ratio of the length of at least the subset of the inner spacers to the thickness of at least the subset of the plurality of portions of the gate structure is in a range of approximately 1.05 to approximately 1.5”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Chiang teaches
wherein a ratio of the length of at least the subset of the inner spacers to the thickness of at least the subset of the plurality of portions of the gate structure is in a range of approximately 1.05 to approximately 1.5 (see e.g., Each sacrificial layer 206, eventually removed and replaced with metal gate stack 252, has a thickness from about 2nm to about 6nm. The inner spacers, including the first inner spacer layer 240 and second inner spacer layer 242, formed in the inner spacer recess 236 may have a height of 5nm to 20nm. The disclosed dimensional ranges encompass, for example, an inner spacer vertical height of approximately 5nm and an adjacent gate portion thickness of approximately 4nm. The resulting ratio is 5nm / 4nm=1.25 which falls within the claimed range of approximately 1.05 to approximately 1.5, Paras [0020], [0049], Figures 21-22).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Chiang’s teachings of wherein a ratio of the length of at least the subset of the inner spacers to the thickness of at least the subset of the plurality of portions of the gate structure is in a range of approximately 1.05 to approximately 1.5 in the device of Cho provide suitable dielectric isolation between gate and source/drain region while reducing parasitic capacitance and maintaining a desired channel thickness.
Regarding claim 3, Cho, as modified by Chiang, teaches the limitations of claim 1 as mentioned above. Cho does not explicitly teach
“wherein a ratio of the thickness of the plurality of nanostructure channels to the thickness of at least the subset of the plurality of portions of the gate structure is in a range of approximately 1.2 to approximately 1.8”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Chiang teaches
wherein a ratio of the thickness of the plurality of nanostructure channels to the thickness of at least the subset of the plurality of portions of the gate structure is in a range of approximately 1.2 to approximately 1.8 (see e.g., Each channel layer 208 has a thickness ranging from about 6nm to about 12nm. The inner spacers, including the first inner spacer layer 240 and second inner spacer layer 242, formed in the inner spacer recess 236 may have a height of 5nm to 20nm. The disclosed dimensional ranges encompass, for example, an inner spacer vertical height of approximately 6nm and a channel with a thickness of approximately 9nm. The resulting ratio is 9nm / 6nm=1.5 which falls within the claimed range of approximately 1.2 to approximately 1.8, Paras [0020], [0049], Figures 21-22).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Chiang’s teachings of wherein a ratio of the thickness of the plurality of nanostructure channels to the thickness of at least the subset of the plurality of portions of the gate structure is in a range of approximately 1.2 to approximately 1.8 in the device of Cho provide suitable dielectric isolation between gate and source/drain region while reducing parasitic capacitance and maintaining a desired channel thickness.
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0381546 A1; hereafter Cho) in view of Chiang et al. (US 2020/0381545 A1; hereafter Chiang) and further in view of Yang et al. (US 2019/0067490 A1; hereafter Yang).
Regarding claim 4, Cho, as modified by Chiang, teaches the limitations of claim 1 as mentioned above. Cho further teaches
wherein the plurality of nanostructure channels comprises:
a first nanostructure channel above the portion of the fin structure (see e.g., the bottommost semiconductor pattern 132a above the active region 100a, Figure 35);
a second nanostructure channel above the first nanostructure channel; and (see e.g., the second semiconductor pattern 132a from the bottom, Figure 35)
a third nanostructure channel above the second nanostructure channel (see e.g., the third semiconductor pattern 132a from the bottom, Figure 35),
wherein the source/drain region comprises:
a first layer formed ….. over the plurality of inner spacers; and
a second layer formed over the first layer, wherein the first layer is continuous between the first nanostructure channel and the third nanostructure channel (see e.g., first semiconductor layer 150 contacting the sidewalls of the semiconductor patterns 132a and the first spacers 144, and the upper surface of the active region 100a. The second semiconductor layer 152 formed on the first semiconductor layer 150, Paras [0053], [0059], Figure 35).
Cho does not explicitly teach
“a first layer formed over a buffer layer”
In a similar field of endeavor Yang teaches
a first layer formed over a buffer layer (see e.g., a multilayer source/drain structure including layers 107a-107d formed over the interfacial layer 106, Paras [0031], [0032], Figure 2)
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Yang’s teachings of a first layer formed over a buffer layer in the device of Cho to facilitate controlled epitaxial growth and formation of the source/drain structure.
Regarding claim 5, Cho, as modified by Chiang and Yang, teaches the limitations of claim 4 as mentioned above. Cho does not explicitly teach
“wherein a first depth of the first layer relative to a center of the source/drain region, at a height of the third nanostructure channel, is greater relative to a second depth of the first layer relative to the center of the source/drain region at a height of the second nanostructure channel”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
Cho teaches the shape of the first semiconductor layer 150 may vary depending upon the process conditions of the epitaxial growth process. The first semiconductor layer 150a may be a non-uniform layer with thickness varying along the semiconductor patterns 132a and the first spacers 144 (see e.g., Figure 3). The first semiconductor layer functions as a source/drain extension region of an NOMOS or PMOS transistor (see e.g., Paras [0056], [0057], [0114]).
Cho, however, does not explicitly recite that the lateral extent of the first semiconductor layer adjacent the upper nanostructured channel is greater than the lateral extent of the first semiconductor layer adjacent a lower nanostructured channel. Accordingly, the relative lateral extent of the first semiconductor layer at the respective channel heights would have been a known controllable epitaxial growth parameter.
Therefore, it would have been obvious to one skilled in art at time the invention was effectively field to optimize and provide greater thickness of the first epitaxial layer near the upper portion of the source/drain region where such a profile was desired to adjust the selective epitaxial growth conditions to obtain a desired non-uniform source/drain extension profile including a greater lateral extent adjacent an upper channel than adjacent a lower channel as a routine optimization of the source/drain extension geometry for the desired device characteristics.
Regarding claim 6, Cho, as modified by Chiang and Yang, teaches the limitations of claim 4 as mentioned above. Cho further teaches
wherein the first layer is continuous along opposing sidewalls of the second layer and is continuous along a bottom of the second layer between the opposing sidewalls (see e.g., first semiconductor layer 150 contacting the sidewalls of the semiconductor patterns 132a and the first spacers 144, and the upper surface of the active region 100a, Para [0053], [0059], Figure 35).
Regarding claim 7, Cho, as modified by Chiang and Yang, teaches the limitations of claim 4 as mentioned above. Cho further teaches
wherein a doping concentration of the second layer is greater relative to a doping concentration of the first layer (see e.g., the second impurity concentration of the second semiconductor layer 152 is higher than the first impurity concentration of the first semiconductor layer 150, Paras [0055], [0059], Figure 35).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0381546 A1; hereafter Cho) in view of Chiang et al. (US 2020/0381545 A1; hereafter Chiang) and Yang et al. (US 2019/0067490 A1; hereafter Yang) and further in view of Jang et al. (US 2020/0220018 A1; hereafter Jang).
Regarding claim 8, Cho, as modified by Chiang and Yang, teaches the limitations of claim 4 as mentioned above. Cho does not explicitly teach
“wherein a first width of the first layer, between a nanostructure channel of the plurality of nanostructure channels and the second layer, is greater relative to a second width of the first layer between an inner spacer of the plurality of inner spacers and the second layer”.
In a similar field of endeavor Jang teaches
wherein a first width of the first layer, between a nanostructure channel of the plurality of nanostructure channels and the second layer, is greater relative to a second width of the first layer between an inner spacer of the plurality of inner spacers and the second layer (see e.g., the first epitaxial layer 152b has a third maximum thickness T3 and a fifth maximum thickness T5. The third thickness T3 is from the exterior surface of the channel layer 141 to the exterior surface of the first epitaxial layer 152b. The fifth thickness T5 is from the exterior surface of the inner spacer to the exterior surface of the first epitaxial layer 152b. The third thickness T3 is greater than the fifth thickness T5, Para [0062], Figures 7-8).
Therefore, it would have been obvious to one skilled in the art at time the invention was effectively filed to implement Jang’s teachings of wherein a first width of the first layer, between a nanostructure channel of the plurality of nanostructure channels and the second layer, is greater relative to a second width of the first layer between an inner spacer of the plurality of inner spacers and the second layer in the device of Cho as it would be a matter of routine optimization to enhance structural integrity and performance of the semiconductor device.
Regarding claim 9, Cho, as modified by Chiang, Yang and Jang, teaches the limitations of claim 8 as mentioned above. Cho does not explicitly teach
“wherein a ratio of the first width to the second width is in a range of approximately 1.2:1 to approximately 2:1”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Jang teaches that the channel-side thickness T3 of the first epitaxial layer 152b is greater than its spacer-side thickness T5. Jang further teaches that the structure of first epitaxial layer 152b may be controlled by adjusting the growth direction, growth thickness and related epitaxial growth conditions (see e.g., Para [0062], Figures 7-8).
Jang does not explicitly disclose that the ratio T3/T5 is within the claimed range of approximately 1.2:1 to approximately 2:1, Jang identifies the relative thickness of the first epitaxial at the channel and inner spacer surfaces as a parameter controllable through known epitaxial growth parameters. Therefore, the ratio between T3 and T5 would have been a result effective variable subject to routine optimization.
Therefore, it would have been obvious to one skilled in art at time the invention was effectively filed to optimize the known growth direction and growth thickness of the first epitaxial layer so that the channel-side width is approximately 1.2 to 2 times the spacer-side width to achieve a desired non-uniform source/drain epitaxial profile.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0381546 A1; hereafter Cho) in view of Kim et al. (US 2021/0367036 A1; hereafter Kim).
Regarding claim 12, Cho, as modified, in claim 10 does not explicitly teach
“wherein a height of a top surface of the second doped semiconductor layer and a height of a top surface of a top-most channel of the first plurality of nanostructure channels are approximately equal”.
In a similar field of endeavor Kim teaches
wherein a height of a top surface of the second doped semiconductor layer and a height of a top surface of a top-most channel of the first plurality of nanostructure channels are approximately equal (see e.g., a channel pattern including first, second and third semiconductor patterns SP1, SP2 and SP3 that are sequentially stacked wherein third semiconductor pattern SP3 is the top most semiconductor channel. The first and second source/drain patterns SD1 and SD2 may be epitaxial patterns, which are formed by a selective epitaxial growth process. As an example, each of the first and second source/drain patterns SD1 and SD2 may have a top surface that is located at substantially the same level as a top surface of the third semiconductor pattern SP3. Each of the first source/drain patterns SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2, which are sequentially stacked. Thus, the top surface of the second semiconductor layer SEL2 corresponds to the top surface of the source/drain pattern, Paras [0039], [0043], [0045], Figures 2A and 2B).
Therefore, it would have been obvious to one skilled in art at time the invention was effectively filed to implement Kim’s teachings of wherein a height of a top surface of the second doped semiconductor layer and a height of a top surface of a top-most channel of the first plurality of nanostructure channels are approximately equal in the device of Cho as such configuration represents a known source/drain epitaxial growth profile in substantially the same stacked channel transistor architecture.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0381546 A1; hereafter Cho) in view of Yang et al. (US 2019/0067490 A1; hereafter Yang).
Regarding claim 14, Cho, as modified, in claim 10 does not explicitly teach
“wherein a height of a top surface of the second doped semiconductor layer is less than a height of a top surface of a top-most channel of the first plurality of nanostructure channels”.
In a similar field of endeavor Yang teaches
wherein a height of a top surface of the second doped semiconductor layer is less than a height of a top surface of a top-most channel of the first plurality of nanostructure channels (see e.g., a plurality of vertically stacked channel layers 120 and embedded source/drain layers 107 adjacent the channel layers. The first epitaxial layer107b and second epitaxial layer 107c have upper surface positioned below the top surface of the uppermost channel layer 120, Paras [0032] – [0035], Figure 2).
Therefore, it would have been obvious to one skilled in art at time the invention was effectively filed to implement Yang’s teachings of wherein a height of a top surface of the second doped semiconductor layer is less than a height of a top surface of a top-most channel of the first plurality of nanostructure channels in the device of Cho to predictably provide a desired multilayer source/drain profile and independently control the material composition and vertical extent of the respective source/drain layers.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0381546 A1; hereafter Cho) in view of Jang et al. (US 2020/0220018 A1; hereafter Jang).
Regarding claim 15, Cho, as modified in claim 10 further teaches
wherein the first doped semiconductor layer and the second doped semiconductor layer comprise a same semiconductor material (see e.g., the first and second semiconductor layers 150 and 152 respectively may be formed of silicon and doped with n-type impurities such as phosphor or arsenic for an NMOS transistor, Paras [0056], [0062], Figure 35);
wherein the first doped semiconductor layer comprises a first n-type dopant (see e.g., first semiconductor layer 150 doped with phosphorus or arsenic, Para [0056]);
wherein the second doped semiconductor comprises a second n-type dopant; and (see e.g., second semiconductor layer 152 may be doped with phosphorus or arsenic, Para [0062])
Cho does not explicitly teach
“wherein the first n-type dopant and the second n-type dopant are different n-type dopants”.
In a similar field of endeavor Jang teaches
wherein the first n-type dopant and the second n-type dopant are different n-type dopants (see e.g., the first epitaxial layer 152 may be a SiP or SiAs epitaxial layer, and the second epitaxial layer 154 may be a SiP epitaxial layer. Accordingly, selection of SiAs for the first epitaxial layer 152 and SiP for the second epitaxial layer 154 provides first and second doped semiconductor layers comprising the same underlying semiconductor material but having different n-type dopants namely arsenic and phosphorus, Para [0034], Figures 7-8).
Therefore, it would have been obvious to one skilled in art at time the invention was effectively filed to implement Jang’s teachings of wherein the first n-type dopant and the second n-type dopant are different n-type dopants in the device of Cho for reducing or preventing short-channel effects associated with dopant diffusion while permitting the second epitaxial layer to provide a more highly doped source/drain region.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0381546 A1; hereafter Cho) in view of Chen et al. (US 2013/0207166 A1; hereafter Chen).
Regarding claim 16, Cho, as modified in claim 10 further teaches
wherein the first doped semiconductor layer and the second doped semiconductor layer comprise a same semiconductor material; and (see e.g., the second semiconductor layer 152 may be doped with impurities to have a conductivity type the same as a conductivity type of impurities of the first semiconductor layer 150. Also, the second semiconductor layer 152 may include a material (or set of materials) the same as a material (or set of materials) of the first semiconductor layer 150. The first semiconductor layer 150 and the second semiconductor layer 152 includes silicon-germanium doped with p-type impurities for a PMOS transistor, Paras [0057], [0060], [0063], Figure 35)
wherein the first doped semiconductor layer and the second doped semiconductor layer comprise a same p-type dopant (see e.g., The first semiconductor layer 150 and the second semiconductor layer 152 maybe doped with p-type impurities including boron, Para [0057], Figure 35).
Chen teaches using boron as p-type impurity for the source/drain silicon germanium epitaxial layers 27 and 35 (see e.g., Paras [0029], [0031], Figure 5).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to use boron as the p-type impurity in both of Cho’s same material p-type semiconductor layers 150 and 152 as taught by Chen because boron was a known p-type dopant for SiGe source/drain epitaxial material. Such a selection would provide the desired p-type conductivity in both SiGe semiconductor layers using the same known dopant/material system and would have yielded predictable results.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0381546 A1; hereafter Cho) in view of Yang et al. (US 2019/0067490 A1; hereafter Yang).
Regarding claim 17, Cho teaches a semiconductor device (see e.g., semiconductor device of Figures 3, 35), comprising:
a plurality of nanostructure channels arranged in a direction that is approximately perpendicular to a substrate of a semiconductor device (see e.g., a plurality of semiconductor patterns 132a vertically stacked above the substrate 100 and serves as multichannel regions of the transistor, Paras [0027], [0030], Figure 35);
a source/drain region laterally adjacent to the plurality of nanostructure channels; and (see e.g., source/drain region 150/152 adjacent to the semiconductor patterns 132a, Paras [0053], [0059], Figure 35)
a plurality of inner spacers laterally adjacent to the source/drain region and vertically alternating with ends of the plurality of nanostructure channels (see e.g., first spacers 144 laterally adjacent the source/drain region 150/152 and vertically alternating with ends of the plurality of semiconductor patterns 132a, Para [0047], Figure 35),
wherein the source/drain region comprises:
a first doped semiconductor layer continuously extending along the ends of the plurality of nanostructure channels; and (see e.g., The first semiconductor layer 150 may contact the sidewalls of the semiconductor patterns 132a and the first spacers 144 and the upper surface of the active region 100a. The first semiconductor layer 150 may have a connected shape, and be continuously formed (i.e., to have a continuously connected shape), along the sidewalls of the semiconductor patterns 132a and the first spacers 144 and the upper surface of the active region 100a, Para [0053], Figure 35)
a second doped semiconductor layer on the first doped semiconductor layer (see e.g., second semiconductor layer 152 formed on the first semiconductor layer 150, Para [0059], Figure 35),
wherein a dopant concentration in the second doped semiconductor layer and a dopant concentration in the first doped semiconductor layer are different dopant concentrations (see e.g., the second semiconductor layer 152 is doped with second impurities to have a second impurity concentration. The first semiconductor layer 150 is doped with first impurities to have a first impurity concentration. The second impurity concentration is higher than the first impurity concentration, Para [0059], Figure 35).
Cho does not explicitly teach
“a semiconductor buffer layer located at a lower vertical position in the semiconductor device than a top surface of a bottom-most nanostructure channel of the plurality of nanostructure channels;”
In a similar field of endeavor Young teaches
a semiconductor buffer layer located at a lower vertical position in the semiconductor device than a top surface of a bottom-most nanostructure channel of the plurality of nanostructure channels (see e.g., interfacial layer 106 comprises a semiconductor material and is disposed adjacent substrate 101/protrusion 104 beneath the vertically stacked channel layers 120. As shown in Figure 2 the interfacial layer 106 is located vertically below the top surface of the bottommost channel layer 120, Para [0033], Figure 2);
Therefore, it would have been obvious to one skilled in art at time the invention was effectively filed to implement Young’s teachings of a semiconductor buffer layer located at a lower vertical position in the semiconductor device than a top surface of a bottom-most nanostructure channel of the plurality of nanostructure channels in the device of Cho to provide an appropriate semiconductor interface beneath the subsequently formed source/drain epitaxial layers and thereby facilitate controlled epitaxial formation of source/drain region.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0381546 A1; hereafter Cho) in view of Yang et al. (US 2019/0067490 A1; hereafter Yang) and further in view Xie et al. (US 2020/0365687 A1; hereafter Xie).
Regarding claim 18, Cho, as modified by Young, teaches the limitations of claim 17 as mentioned above. Cho does not explicitly teach
“wherein the semiconductor buffer layer includes a (100) grain orientation”.
In a similar field of endeavor Xie teaches
wherein the semiconductor buffer layer includes a (100) grain orientation (see e.g., the source and drain regions 704 can be formed by epitaxial growth from the <100> surface (i.e., the top surface) of the semiconductor buffer layer 702, epitaxial growth from a <100> surface is much faster and will dominate the overall epitaxial growth process, Para [0059], Figure 7).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Xie’s teachings of wherein the semiconductor buffer layer includes a (100) grain orientation in the method of Yeh to improve the source/drain epitaxial growth quality and process control.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0381546 A1; hereafter Cho) in view of Yang et al. (US 2019/0067490 A1; hereafter Yang) and further in view Jang et al. (US 2020/0220018 A1; hereafter Jang).
Regarding claim 19, Cho, as modified by Young, teaches the limitations of claim 17 as mentioned above. Cho further teaches
wherein the first doped semiconductor layer comprises an arsenic-doped silicon (SiAs) or a boron-doped silicon germanium (SiGe:B); and (see e.g., first semiconductor layer 150 includes silicon doped with n-type impurities such as arsenic or phosphorus for an NMOS transistor or includes silicon germanium doped with p-type impurities such as boron for a PMOS transistor, Paras [0056], [0057], Figure 35)
Cho does not explicitly teach
“wherein the second doped semiconductor layer comprises a phosphor-doped silicon (SiP) or a boron-doped silicon germanium (SiGe:B)”
In a similar field of endeavor Jang teaches
wherein the second doped semiconductor layer comprises a phosphor-doped silicon (SiP) or a boron-doped silicon germanium (SiGe:B) (see e.g., the first epitaxial layer 152 may be a SiAs epitaxial layer. The second epitaxial layer 154 may be a SiP epitaxial layer, Para [0034], Figures 7-8).
Therefore, it would have been obvious to one skilled in art at time the invention was effectively filed to implement Jang’s teachings of wherein the second doped semiconductor layer comprises a phosphor-doped silicon (SiP) or a boron-doped silicon germanium (SiGe:B) to provide the desired conductivity type and dopant concentration profile in the source/drain region while maintaining compatibility with the surrounding channel structure and epitaxial fabrication process.
Cho does not explicitly teach
“wherein the semiconductor buffer layer comprises silicon (Si) or silicon germanium (SiGe);”
In a similar field of endeavor Young teaches
wherein the semiconductor buffer layer comprises silicon (Si) or silicon germanium (SiGe) (see e.g., the interfacial layer 106 may include silicon germanium, Paras [0032], [0033], Figure 35);
Therefore, it would have been obvious to one skilled in art at time the invention was effectively filed to implement Young’s teachings wherein the semiconductor buffer layer comprises silicon (Si) or silicon germanium (SiGe) in the device of Cho to provide a compatible semiconductor interface for epitaxial source/drain growth and would have yielded predictable results in the similar stacked channel semiconductor structure.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2020/0381546 A1; hereafter Cho) in view of Yang et al. (US 2019/0067490 A1; hereafter Yang) and further in view Chen et al. (US 2013/0207166 A1; hereafter Chen).
Regarding claim 20, Cho, as modified by Young, teaches the limitations of claim 17 as mentioned above. Cho does not explicitly teach
“wherein the source/drain region further comprises:
a semiconductor capping layer on the second doped semiconductor layer, wherein the semiconductor capping layer comprises a phosphor-doped silicon (SiP) or a boron-doped silicon germanium (SiGe:B)”.
In a similar field of endeavor Young teaches
wherein the source/drain region further comprises:
a semiconductor capping layer on the second doped semiconductor layer, wherein the semiconductor capping layer comprises a phosphor-doped silicon (SiP) or a boron-doped silicon germanium (SiGe:B) (see e.g., a multilayer epitaxial source/drain region including first, second and third epitaxial layers 107b, 107c and 107d wherein the third epitaxial layer 107d is formed over the second epitaxial layer 107c. The third epitaxial layer 107d may include SiGe, with 50% to 60% at% Ge, and doped with p-type impurities, Paras [0032], [0033], [0034], Figure 2).
Chen teaches boron as a suitable p-type dopant for silicon germanium epitaxial cap layer 45 (see e.g., Para [0031], Figure 5).
Therefore, it would have been obvious to one skilled in art at time the invention was effectively filed to implement wherein the source/drain region further comprises: a semiconductor capping layer on the second doped semiconductor layer, wherein the semiconductor capping layer comprises a phosphor-doped silicon (SiP) or a boron-doped silicon germanium (SiGe:B) in the device of Cho to reduce contact resistance and sheet resistance at the surface for enhanced contact performance.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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